nxp,s32ze-pinctrl

Vendor: NXP Semiconductors N.V.

Description

NXP S32 pinctrl node for S32Z/E SoCs.

The NXP S32 pin controller is a singleton node responsible for controlling
the pin function selection and pin properties. This node, labeled 'pinctrl' in
the SoC's devicetree, will define pin configurations in pin groups. Each group
within the pin configuration defines the pin configuration for a peripheral,
and each numbered subgroup in the pin group defines all the pins for that
peripheral with the same configuration properties. The 'pinmux' property in
a group selects the pins to be configured, and the remaining properties set
configuration values for those pins.

For example, to configure the pinmux for UART0, modify the 'pinctrl' from your
board or application devicetree overlay as follows:

  /* Include the SoC package header containing the predefined pins definitions */
  #include <nxp/s32/S32Z27-BGA594-pinctrl.h>

  &pinctrl {
    uart0_default: uart0_default {
      group1 {
        pinmux = <PB10_LIN_0_TX>;
        output-enable;
      };
      group2 {
        pinmux = <PB11_LIN_0_RX>;
        input-enable;
      };
    };
  };

The 'uart0_default' node contains the pin configurations for a particular state
of a device. The 'default' state is the active state. Other states for the same
device can be specified in separate child nodes of 'pinctrl'.

In addition to 'pinmux' property, each group can contain other properties such as
'bias-pull-up' or 'slew-rate' that will be applied to all the pins defined in
'pinmux' array. To enable the input buffer use 'input-enable' and to enable the
output buffer use 'output-enable'.

To link the pin configurations with UART0 device, use pinctrl-N property in the
device node, where 'N' is the zero-based state index (0 is the default state).
Following previous example:

  &uart0 {
    pinctrl-0 = <&uart0_default>;
    pinctrl-names = "default";
    status = "okay";
  };

If only the required properties are supplied, the pin configuration register
will be assigned the following reset values:
  - input and output buffers disabled
  - internal pull not enabled
  - open drain disabled
  - slew rate 4 (see description in property below).

Additionally, Safe Mode is always disabled (reset value) and configuration that
only applies to LVDS pads, which are not supported, default to reset values:
  - termination resistor disabled
  - receiver single ended
  - current reference control disabled
  - Rx current boost disabled.

Properties

Top level properties

These property descriptions apply to “nxp,s32ze-pinctrl” nodes themselves. This page also describes child node properties in the following sections.

Node specific propertiesDeprecated node specific propertiesBase properties

Properties not inherited from the base binding file.

(None)

Grandchild node properties

Name	Type	Details
bias-pull-up	boolean	enable pull-up resistor
bias-pull-down	boolean	enable pull-down resistor
drive-open-drain	boolean	drive with open drain (hardware AND)
input-enable	boolean	enable input on pin (e.g. enable an input buffer, no effect on output)
output-enable	boolean	enable output on a pin without actively driving it (e.g. enable an output buffer)
slew-rate	int	Slew rate control. Reset value is 4. - For 3.3 V / 1.8 V FAST pads: 0: FMAX_3318 = 208 MHz (at 1.8 V), 166 MHz (at 3.3 V) 4: FMAX_3318 = 166 MHz (at 1.8 V), 150 MHz (at 3.3 V) 5: FMAX_3318 = 150 MHz (at 1.8 V), 133 MHz (at 3.3 V) 6: FMAX_3318 = 133 MHz (at 1.8 V), 100 MHz (at 3.3 V) 7: FMAX_3318 = 100 MHz (at 1.8 V), 83 MHz (at 3.3 V) - For 1.8 V GPIO pads: 0: FMAX_18 = 208 MHz 4: FMAX_18 = 150 MHz 5: FMAX_18 = 133 MHz 6: FMAX_18 = 100 MHz 7: FMAX_18 = 50 MHz - For 3.3 V GPIO pads: 0: Reserved 4: FMAX_33 = 50 MHz 5: FMAX_33 = 50 MHz 6: FMAX_33 = 50 MHz 7: FMAX_33 = 1 MHz Default value: 4 Legal values: 0, 4, 5, 6, 7
pinmux	array	An array of pins sharing the same group properties. The pins must be defined using the macros from the SoC package header. These macros encode all the pin muxing information in a 32-bit value. This property is required.