silabs,dbus-pinctrl
Vendor: Silicon Laboratories
Note
An implementation of a driver matching this compatible is available in drivers/pinctrl/pinctrl_silabs_dbus.c.
Description
The Silabs pin controller is a singleton node responsible for controlling
pin function selection and pin properties. For example, you can use this
node to route USART0 RX to pin PA1 and enable the pull-up resistor on the
pin. This pin controller is used for devices that use DBUS (Digital Bus)
for alternate function configuration, including Series 2 devices. It is
also capable of ABUS (Analog Bus) allocation.
The pinctrl settings are referenced in a device tree peripheral node. For
example when configuring a USART:
&usart0 {
compatible = "silabs,gecko-usart";
pinctrl-0 = <&usart0_default>;
pinctrl-names = "default";
}
pinctrl-0 is a phandle that stores the pin settings for the peripheral, in
this example &usart0_default. This phandle is defined as a child node of the
'pinctrl' node, typically in a board-pinctrl.dtsi file in the board
directory or a device tree overlay in the application:
&pinctrl {
/* Configuration for USART0 peripheral, default state */
usart0_default: usart0_default {
/* Group of output pins with shared properties (name is arbitrary) */
group0 {
/* Configure PA8 as USART0 TX in GPIO DBUS */
pins = <USART0_TX_PA8>;
/* Configure GPIO to push-pull mode */
drive-push-pull;
/* Set DOUT high */
output-high;
};
/* Group of input pins with shared properties (name is arbitrary) */
group1 {
/* Configure PA9 as USART0 RX in GPIO DBUS */
pins = <USART0_RX_PA9>;
/* Configure GPIO to input mode */
input-enable;
/* Enable input glitch filter */
silabs,input-filter;
};
};
};
The 'usart0_default' child node encodes the pin configurations for a
particular state of the device, the default (active) state.
Pin configurations are organized in groups within each child node. Each
group can specify a list of pin function selections in the `pins` property,
that all will be configured with the same GPIO mode as given by the rest
of the properties on the group.
The possible pin properties are as follows:
- input-disable: Configure GPIO to disabled mode. Setting this property is
optional, as pins are disabled by default. If the "Input
disabled with pull-up" mode is desired, the property must
be set in combination with bias-pull-up.
- input-enable: Configure GPIO to input mode.
- drive-push-pull: Configure GPIO to push-pull mode.
- drive-open-drain: Configure GPIO to open-drain (wired-AND) mode.
- drive-open-source: Configure GPIO to open-source (wired-OR) mode.
Only one of the above properties must be set at a time, as they are mutually
exclusive. Additional properties may be combined with the above ones:
- bias-pull-down: Enable pull-down resistor. Allowed in input-enable and
drive-open-source modes.
- bias-pull-up: Enable pull-up resistor. Allowed in input-disable,
input-enable and drive-open-drain modes.
- output-high: Drive GPIO high. Allowed in drive-push-pull mode.
- output-low: Drive GPIO low. Allowed in drive-push-pull mode. Setting
this property is optional, leaving it out has the same effect.
- silabs,input-filter: Enable input glitch filter. Allowed in input-enable
and drive-open-drain modes.
- silabs,alternate-port-control: Use alternate port control settings.
Allowed in drive-push-pull and
drive-open-drain modes.
ABUS allocation is performed using the 'silabs,analog-bus' property. This
property takes an array of buses to allocate. Example:
&pinctrl {
iadc0_default: iadc0_default {
group0 {
/* Allocate even bus 0 and odd bus 1 from GPIO port A for ADC use */
silabs,analog-bus = <ABUS_AEVEN0_IADC0>, <ABUS_AODD1_IADC0>;
}
};
};
A given group may contain a mix of analog bus allocations and digital pin
selections. Digital pin properties only apply to digital pins. Analog input
selection is not done through the pin controller, this is done in the devicetree
node for the respective peripheral using properties such as 'zephyr,input-positive'
for ADC.
Properties
Top level properties
These property descriptions apply to “silabs,dbus-pinctrl” nodes themselves. This page also describes child node properties in the following sections.
Node specific properties
Properties not inherited from the base binding file.
(None)
Deprecated node specific properties
Deprecated properties not inherited from the base binding file.
(None)
Base properties
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “silabs,dbus-pinctrl” compatible.
Name |
Type |
Details |
|---|---|---|
|
|
Indicates the operational status of the hardware or other
resource that the node represents. In particular:
- "okay" means the resource is operational and, for example,
can be used by device drivers
- "disabled" means the resource is not operational and the system
should treat it as if it is not present
For details, see "2.3.4 status" in Devicetree Specification v0.4.
Legal values: See Important properties for more information. |
|
|
This property is a list of strings that essentially define what
type of hardware or other resource this devicetree node
represents. Each device driver checks for specific compatible
property values to find the devicetree nodes that represent
resources that the driver should manage.
The recommended format is "vendor,device", The "vendor" part is
an abbreviated name of the vendor. The "device" is usually from
the datasheet.
The compatible property can have multiple values, ordered from
most- to least-specific. Having additional values is useful when the
device is a specific instance of a more general family, to allow the
system to match the most specific driver available.
For details, see "2.3.1 compatible" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
|
|
Information used to address the device. The value is specific to
the device (i.e. is different depending on the compatible
property).
The "reg" property is typically a sequence of (address, length) pairs.
Each pair is called a "register block". Values are
conventionally written in hex.
For details, see "2.3.6 reg" in Devicetree Specification v0.4.
See Important properties for more information. |
|
|
Optional names given to each register block in the "reg" property.
For example:
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
uart@1000 {
reg = <0x1000 0x2000>, <0x3000 0x4000>;
reg-names = "foo", "bar";
};
};
};
The uart@1000 node has two register blocks:
- one with base address 0x1000, size 0x2000, and name "foo"
- another with base address 0x3000, size 0x4000, and name "bar"
|
|
|
Information about interrupts generated by the device, encoded as an array
of one or more interrupt specifiers. The format of the data in this property
varies by where the device appears in the interrupt tree. Devices with the same
"interrupt-parent" will use the same format in their interrupts properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
See Important properties for more information. |
|
|
Extended interrupt specifier for device, used as an alternative to
the "interrupts" property.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
|
|
|
Optional names given to each interrupt generated by a device.
The interrupts themselves are defined in either "interrupts" or
"interrupts-extended" properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
|
|
|
If present, this refers to the node which handles interrupts generated
by this device.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
|
|
|
Human readable string describing the device. Use of this property is
deprecated except as needed on a case-by-case basis.
For details, see "4.1.2 Miscellaneous Properties" in Devicetree
Specification v0.4.
See Important properties for more information. |
|
|
Information about the device's clock providers. In general, this property
should follow conventions established in the dt-schema binding:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml
|
|
|
Optional names given to each clock provider in the "clocks" property.
|
|
|
This property encodes the number of <u32> cells used by address fields
in "reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
|
|
|
This property encodes the number of <u32> cells used by size fields in
"reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
|
|
|
DMA channel specifiers relevant to the device.
|
|
|
Optional names given to the DMA channel specifiers in the "dmas" property.
|
|
|
IO channel specifiers relevant to the device.
|
|
|
Optional names given to the IO channel specifiers in the "io-channels" property.
|
|
|
Mailbox / IPM channel specifiers relevant to the device.
|
|
|
Optional names given to the mbox specifiers in the "mboxes" property.
|
|
|
Power domain specifiers relevant to the device.
|
|
|
Optional names given to the power domain specifiers in the "power-domains" property.
|
|
|
Number of cells in power-domains property
|
|
|
Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
|
|
|
Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
|
|
|
Automatically configure the device for runtime power management after the
init function runs.
|
|
|
List of power states that will disable this device power.
|
Grandchild node properties
Name |
Type |
Details |
|---|---|---|
|
|
An array of pins sharing the same group properties. The pins should be
defined using the <peripheral>_<signal>_<pin> macros available from
the SoC DeviceTree files.
|
|
|
Enable input glitch filter on this pin. May be used in input-enable
and drive-open-drain modes.
|
|
|
Use Alternate Port Control settings for Slew Rate and Input Disable
for this pin. May be used in drive-push-pull and drive-open-drain
modes.
|
|
|
Assign one or more analog buses to the given GPIO port. The bus should
be defined using the ABUS_<bus>_<peripheral> macros available from the
SoC DeviceTree files.
|
|
|
enable pull-up resistor
|
|
|
enable pull-down resistor
|
|
|
drive actively high and low
|
|
|
drive with open drain (hardware AND)
|
|
|
drive with open source (hardware OR)
|
|
|
enable input on pin (e.g. enable an input buffer, no effect on output)
|
|
|
disable input on pin (e.g. disable an input buffer, no effect on output)
|
|
|
set the pin to output mode with low level
|
|
|
set the pin to output mode with high level
|