espressif,esp32-mcpwm

Vendor: Espressif Systems

Note

An implementation of a driver matching this compatible is available in drivers/pwm/pwm_mc_esp32.c.

Description

Espressif's Motor Control Pulse Width Modulator (MCPWM) controller Node

The MCPWM peripheral is intended for motor and power control.
It provides six PWM outputs that can be set up to operate in several topologies

ESP32 contains two MCPWM peripherals: MCPWM0 and MCPWM1

Each MCPWM peripheral has one clock divider (prescaler), three PWM timers, three PWM operators,
and a capture module.

Every PWM operator has two PWM outputs: PWMxA and PWMxB. They can work independently, in symmetric
and asymmetric configuration. MCPWMxA and MCPWMxB will share the same timer, thus having the same
operating frequency.

The driver currently always use the timer x for operator x. Timer 0 will use operator 0 for
PWM0A/B.
Timer 1 will use operator 1 for PWM1A/B, and so on.

Mapping channel ID:
Channel 0 -> Timer 0, Operator 0, output PWM0A
Channel 1 -> Timer 0, Operator 0, output PWM0B
Channel 2 -> Timer 1, Operator 1, output PWM1A
Channel 3 -> Timer 1, Operator 1, output PWM1B
Channel 4 -> Timer 2, Operator 2, output PWM2A
Channel 5 -> Timer 2, Operator 2, output PWM2B
Channel 6 -> Capture 0
Channel 7 -> Capture 1
Channel 8 -> Capture 2

Example: Use PWM0A output and capture 0:

pwm_loopback_0 {
  compatible = "test-pwm-loopback";
  pwms = <&mcpwm0 0 0 PWM_POLARITY_NORMAL>, #Channel 0 -> Output PWM0A
         <&mcpwm0 6 0 PWM_POLARITY_NORMAL>; #Channel 6 -> Capture 0;
};

The mapping between the output PWMxA/B or CaptureX and GPIO is done through pinctrl:

  &mcpwm0 {
    pinctrl-0 = <&mcpwm0_default>;
    pinctrl-names = "default";
  }

The 'mcpwm0_default' node is defined inside the pinctrl node.

  &pinctrl {
    mcpwm0_default: mcpwm0_default {
      group1 {
        pinmux = <MCPWM0_OUT0A_GPIO0>,
          <MCPWM0_OUT0B_GPIO2>,
          <MCPWM0_OUT1A_GPIO4>;
        output-enable;
      };
      group2 {
        pinmux = <MCPWM0_CAP0_GPIO5>;
      };
    };
  };

Note: Check espressif,esp32-pinctrl.yaml for complete documentation regarding pinctrl.

Use the prescale-timerX property to configure the timers:

  &mcpwm0 {
    pinctrl-0 = <&mcpwm0_default>;
    pinctrl-names = "default";
    prescale = <255>;
    prescale-timer0 = <103>;
    prescale-timer1 = <0>;
    prescale-timer2 = <255>;
    status = "okay";
  };

Properties

Node specific properties

Properties not inherited from the base binding file.

Name

Type

Details

prescale

int

 
8 bit timer prescale for the global clock.
Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1).

This property is required.

#pwm-cells

int

 
Number of items to expect in a pwm specifier

This property is required.

Constant value: 3

prescale-timer0

int

 
8 bit timer prescale for timer 0.
Period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1).

prescale-timer1

int

 
8 bit timer prescale for timer 1.
Period of PT1_clk = Period of PWM_clk * (PWM_TIMER1_PRESCALE + 1).

prescale-timer2

int

 
8 bit timer prescale for timer 2.
Period of PT2_clk = Period of PWM_clk * (PWM_TIMER2_PRESCALE + 1).

pinctrl-0

phandles

 
Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

pinctrl-1

phandles

 
Pin configuration/s for the second state. See pinctrl-0.

pinctrl-2

phandles

 
Pin configuration/s for the third state. See pinctrl-0.

pinctrl-3

phandles

 
Pin configuration/s for the fourth state. See pinctrl-0.

pinctrl-4

phandles

 
Pin configuration/s for the fifth state. See pinctrl-0.

pinctrl-names

string-array

 
Names for the provided states. The number of names needs to match the
number of states.

Deprecated node specific properties

Deprecated properties not inherited from the base binding file.

(None)

Base properties

Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “espressif,esp32-mcpwm” compatible.

Name

Type

Details

status

string

 
Indicates the operational status of the hardware or other
resource that the node represents. In particular:

  - "okay" means the resource is operational and, for example,
    can be used by device drivers
  - "disabled" means the resource is not operational and the system
    should treat it as if it is not present

For details, see "2.3.4 status" in Devicetree Specification v0.4.

Legal values: 'ok', 'okay', 'disabled', 'reserved', 'fail', 'fail-sss'

See Important properties for more information.

compatible

string-array

 
This property is a list of strings that essentially define what
type of hardware or other resource this devicetree node
represents. Each device driver checks for specific compatible
property values to find the devicetree nodes that represent
resources that the driver should manage.

The recommended format is "vendor,device", The "vendor" part is
an abbreviated name of the vendor. The "device" is usually from
the datasheet.

The compatible property can have multiple values, ordered from
most- to least-specific. Having additional values is useful when the
device is a specific instance of a more general family, to allow the
system to match the most specific driver available.

For details, see "2.3.1 compatible" in Devicetree Specification v0.4.

This property is required.

See Important properties for more information.

reg

array

 
Information used to address the device. The value is specific to
the device (i.e. is different depending on the compatible
property).

The "reg" property is typically a sequence of (address, length) pairs.
Each pair is called a "register block". Values are
conventionally written in hex.

For details, see "2.3.6 reg" in Devicetree Specification v0.4.

See Important properties for more information.

reg-names

string-array

 
Optional names given to each register block in the "reg" property.
For example:

  / {
       soc {
           #address-cells = <1>;
           #size-cells = <1>;

           uart@1000 {
               reg = <0x1000 0x2000>, <0x3000 0x4000>;
               reg-names = "foo", "bar";
           };
       };
  };

The uart@1000 node has two register blocks:

  - one with base address 0x1000, size 0x2000, and name "foo"
  - another with base address 0x3000, size 0x4000, and name "bar"

interrupts

array

 
Information about interrupts generated by the device, encoded as an array
of one or more interrupt specifiers. The format of the data in this property
varies by where the device appears in the interrupt tree. Devices with the same
"interrupt-parent" will use the same format in their interrupts properties.

For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.

See Important properties for more information.

interrupts-extended

compound

 
Extended interrupt specifier for device, used as an alternative to
the "interrupts" property.

For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.

interrupt-names

string-array

 
Optional names given to each interrupt generated by a device.
The interrupts themselves are defined in either "interrupts" or
"interrupts-extended" properties.

For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.

interrupt-parent

phandle

 
If present, this refers to the node which handles interrupts generated
by this device.

For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.

label

string

 
Human readable string describing the device. Use of this property is
deprecated except as needed on a case-by-case basis.

For details, see "4.1.2 Miscellaneous Properties" in Devicetree
Specification v0.4.

See Important properties for more information.

clocks

phandle-array

 
Information about the device's clock providers. In general, this property
should follow conventions established in the dt-schema binding:

  https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml

clock-names

string-array

 
Optional names given to each clock provider in the "clocks" property.

#address-cells

int

 
This property encodes the number of <u32> cells used by address fields
in "reg" properties in this node's children.

For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.

#size-cells

int

 
This property encodes the number of <u32> cells used by size fields in
"reg" properties in this node's children.

For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.

dmas

phandle-array

 
DMA channel specifiers relevant to the device.

dma-names

string-array

 
Optional names given to the DMA channel specifiers in the "dmas" property.

io-channels

phandle-array

 
IO channel specifiers relevant to the device.

io-channel-names

string-array

 
Optional names given to the IO channel specifiers in the "io-channels" property.

mboxes

phandle-array

 
Mailbox / IPM channel specifiers relevant to the device.

mbox-names

string-array

 
Optional names given to the mbox specifiers in the "mboxes" property.

power-domains

phandle-array

 
Power domain specifiers relevant to the device.

power-domain-names

string-array

 
Optional names given to the power domain specifiers in the "power-domains" property.

#power-domain-cells

int

 
Number of cells in power-domains property

zephyr,deferred-init

boolean

 
Do not initialize device automatically on boot. Device should be manually
initialized using device_init().

wakeup-source

boolean

 
Property to identify that a device can be used as wake up source.

When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.

Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.

zephyr,pm-device-runtime-auto

boolean

 
Automatically configure the device for runtime power management after the
init function runs.

zephyr,disabling-power-states

phandles

 
List of power states that will disable this device power.

Specifier cell names

  • pwm cells: channel, period, flags