nxp,s32-emios-pwm
Vendor: NXP Semiconductors N.V.
Note
An implementation of a driver matching this compatible is available in drivers/pwm/pwm_nxp_s32_emios.c.
Description
NXP S32 eMIOS PWM node for S32 SoCs. Each channel in eMIOS can be configured
to use for PWM operation. There are several PWM modes supported by this module,
some modes only support on channels that have internal counter, some modes
require to use a reference timebase from a master bus.
For example to configuring eMIOS instance 0 with:
- Channel 0 for mode OPWFMB
- Channel 1 for mode OPWMB
- Channel 2 for mode OPWMCB with deadtime inserted at leading edge
- Channel 3 for mode SAIC, use internal timebase with input filter = 2 eMIOS clock
emios0_pwm: pwm {
pwm_0 {
channel = <0>;
pwm-mode = "OPWFMB";
prescaler = <8>;
};
pwm_1 {
channel = <1>;
master-bus = <&emios1_bus_a>;
pwm-mode = "OPWMB";
phase-shift = <100>;
};
pwm_2 {
channel = <2>;
master-bus = <&emios1_bus_b>;
pwm-mode = "OPWMCB_LEAD_EDGE";
dead-time = <100>;
};
pwm_3 {
channel = <3>;
pwm-mode = "SAIC";
prescaler = <8>;
input-filter = <2>;
};
};
OPWMB and OPWMCB modes use reference timebase, the master bus is chosen over
phandle 'master-bus'. Please notice that the devicetree node for master bus
should be enabled and configured for using, please see 'nxp,s32-emios' bindings.
Properties
Top level properties
These property descriptions apply to “nxp,s32-emios-pwm” nodes themselves. This page also describes child node properties in the following sections.
Node specific properties
Properties not inherited from the base binding file.
Name |
Type |
Details |
|---|---|---|
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Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.
This property is required. |
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Names for the provided states. The number of names needs to match the
number of states.
This property is required. |
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Number of items to expect in a pwm specifier
This property is required. Constant value: |
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Pin configuration/s for the second state. See pinctrl-0.
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Pin configuration/s for the third state. See pinctrl-0.
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Pin configuration/s for the fourth state. See pinctrl-0.
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Pin configuration/s for the fifth state. See pinctrl-0.
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Deprecated node specific properties
Deprecated properties not inherited from the base binding file.
(None)
Base properties
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “nxp,s32-emios-pwm” compatible.
Name |
Type |
Details |
|---|---|---|
|
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Indicates the operational status of the hardware or other
resource that the node represents. In particular:
- "okay" means the resource is operational and, for example,
can be used by device drivers
- "disabled" means the resource is not operational and the system
should treat it as if it is not present
For details, see "2.3.4 status" in Devicetree Specification v0.4.
Legal values: See Important properties for more information. |
|
|
This property is a list of strings that essentially define what
type of hardware or other resource this devicetree node
represents. Each device driver checks for specific compatible
property values to find the devicetree nodes that represent
resources that the driver should manage.
The recommended format is "vendor,device", The "vendor" part is
an abbreviated name of the vendor. The "device" is usually from
the datasheet.
The compatible property can have multiple values, ordered from
most- to least-specific. Having additional values is useful when the
device is a specific instance of a more general family, to allow the
system to match the most specific driver available.
For details, see "2.3.1 compatible" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
|
|
Information used to address the device. The value is specific to
the device (i.e. is different depending on the compatible
property).
The "reg" property is typically a sequence of (address, length) pairs.
Each pair is called a "register block". Values are
conventionally written in hex.
For details, see "2.3.6 reg" in Devicetree Specification v0.4.
See Important properties for more information. |
|
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Optional names given to each register block in the "reg" property.
For example:
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
uart@1000 {
reg = <0x1000 0x2000>, <0x3000 0x4000>;
reg-names = "foo", "bar";
};
};
};
The uart@1000 node has two register blocks:
- one with base address 0x1000, size 0x2000, and name "foo"
- another with base address 0x3000, size 0x4000, and name "bar"
|
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Information about interrupts generated by the device, encoded as an array
of one or more interrupt specifiers. The format of the data in this property
varies by where the device appears in the interrupt tree. Devices with the same
"interrupt-parent" will use the same format in their interrupts properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
See Important properties for more information. |
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Extended interrupt specifier for device, used as an alternative to
the "interrupts" property.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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Optional names given to each interrupt generated by a device.
The interrupts themselves are defined in either "interrupts" or
"interrupts-extended" properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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If present, this refers to the node which handles interrupts generated
by this device.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
|
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Human readable string describing the device. Use of this property is
deprecated except as needed on a case-by-case basis.
For details, see "4.1.2 Miscellaneous Properties" in Devicetree
Specification v0.4.
See Important properties for more information. |
|
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Information about the device's clock providers. In general, this property
should follow conventions established in the dt-schema binding:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml
|
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Optional names given to each clock provider in the "clocks" property.
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This property encodes the number of <u32> cells used by address fields
in "reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
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This property encodes the number of <u32> cells used by size fields in
"reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
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DMA channel specifiers relevant to the device.
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Optional names given to the DMA channel specifiers in the "dmas" property.
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IO channel specifiers relevant to the device.
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Optional names given to the IO channel specifiers in the "io-channels" property.
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Mailbox / IPM channel specifiers relevant to the device.
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Optional names given to the mbox specifiers in the "mboxes" property.
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Power domain specifiers relevant to the device.
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Optional names given to the power domain specifiers in the "power-domains" property.
|
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Number of cells in power-domains property
|
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Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
|
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
|
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Automatically configure the device for runtime power management after the
init function runs.
|
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List of power states that will disable this device power.
|
Child node properties
Name |
Type |
Details |
|---|---|---|
|
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eMIOS PWM channel
This property is required. |
|
|
A phandle to master-bus node that will be used as external timebase
for current channel, this can be bypassed if internal counter is used
for PWM operation. A master bus must be used exclusively, such as if
is used as a timebase for a channel in SAIC mode, do not use that
master bus as a timebase for generate PWM pulse.
|
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Select PWM mode:
- OPWFMB: provides waveforms with variable duty cycle and frequency,
this mode uses internal counter.
- OPWMB: generate pulses with programmable leading and trailing
edge placement. The period is determined by period of
an external counter driven in MCB Up Mode. Changing PWM period
at runtime will impact to all channels share the same timebase.
The new period and cycle take effect in next period boundary.
- OPWMCB: generates a center aligned PWM with dead time insertion to the
leading or trailing edge. The period is determined by period of
an external counter driven in MCB Up Down Mode. Changing PWM period
at runtime will impact to all channels share the same timebase,
The new period and cycle take effect in next period boundary.
- SAIC: single action input capture mode, the eMIOS captures events as soon as
they occur. The value of latest captured event is stored and can be read
by software.
This property is required. Legal values: |
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Freeze individual internal counter when the chip enters Debug mode.
|
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Select clock source for internal counter prescaler.
Default value: Legal values: |
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The clock divider for internal counter prescaler.
Legal values: |
|
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Dead time (in ticks) for PWM channel in OPWMCB mode.
|
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Phase Shift (in ticks) for PWM channel in OPWMB mode.
|
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Select the minimum input pulse width, in filter clock cycles that can pass
through the input filter. The filter latency - the difference in time between
the input and the response is three clock edges. Default 0 means the filter
is bypassed. The clock source for programmable input filter is eMIOS clock.
Legal values: |
Specifier cell names
pwm cells: channel, period, flags