adi,max30009 (on spi bus)
Description
MAX30009 Bio-Impedance AFE with SPI connection
Properties
Node specific properties
Properties not inherited from the base binding file.
Name |
Type |
Details |
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Maximum clock frequency of device's SPI interface in Hz
This property is required. |
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Duplex mode, full or half. By default it's always full duplex thus 0
as this is, by far, the most common mode.
Use the macros not the actual enum value, here is the concordance
list (see dt-bindings/spi/spi.h)
0 SPI_FULL_DUPLEX
2048 SPI_HALF_DUPLEX
Default value: Legal values: |
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Motorola or TI frame format. By default it's always Motorola's,
thus 0 as this is, by far, the most common format.
Use the macros not the actual enum value, here is the concordance
list (see dt-bindings/spi/spi.h)
0 SPI_FRAME_FORMAT_MOTOROLA
32768 SPI_FRAME_FORMAT_TI
Default value: Legal values: |
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SPI clock polarity which indicates the clock idle state.
If it is used, the clock idle state is logic high; otherwise, low.
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SPI clock phase that indicates on which edge data is sampled.
If it is used, data is sampled on the second edge; otherwise, on the first edge.
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The device requires least significant bit first data mode.
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In some cases, it is necessary for the master to manage SPI chip select
under software control, so that multiple spi transactions can be performed
without releasing it. A typical use case is variable length SPI packets
where the first spi transaction reads the length and the second spi transaction
reads length bytes.
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The device requires the chip select to be active high.
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Delay in nanoseconds between SPI words.
Default of 0 is special value which will assume to mean half of the SCK period.
Default value: |
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Delay in nanoseconds to be introduced by the controller after CS is asserted.
Also known as enable lead time.
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Delay in nanoseconds to be introduced by the controller before the CS is de-asserted.
Also known as enable lag time.
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GPIO specifier that controls power to the device.
This property should be provided when the device has a dedicated
switch that controls power to the device. The supply state is
entirely the responsibility of the device driver.
Contrast with vin-supply.
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Reference to the regulator that controls power to the device.
The referenced devicetree node must have a regulator compatible.
This property should be provided when device power is supplied
by a shared regulator. The supply state is dependent on the
request status of all devices fed by the regulator.
Contrast with supply-gpios. If both properties are provided
then the regulator must be requested before the supply GPIOS is
set to an active state, and the supply GPIOS must be set to an
inactive state before releasing the regulator.
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Interrupt (INT) pin. The MAX30009 INT output is active low and open-drain
by default; the property value should describe the signal presented to the SoC.
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Specify the FIFO watermark level in frame count.
Default value is the reset value.
Default value: Value range: |
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A_FULL_TYPE sets the A_FULL interrupt behavior. When cleared, A_FULL
reasserts every sample while the almost-full condition persists; when set,
A_FULL asserts once and does not reassert until the FIFO is read and a new
almost-full condition occurs. Cleared at reset.
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FIFO_RO enables FIFO roll-over. When set, the FIFO keeps pushing samples
once full and overwrites the oldest data (write and read pointers both
advance); when cleared, new samples are dropped until the FIFO is read.
Disabled at reset.
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PLL reference clock source (REF_CLK_SEL). "internal" selects one of the
on-chip slow oscillators; "external" selects the clock driven on the FCLK
pin. Defaults to "internal", matching the device reset state.
Default value: Legal values: |
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PLL reference clock frequency in Hz (CLK_FREQ_SEL). When ref-clk-source is
"internal" this selects which on-chip oscillator is used; when "external"
it must match the frequency of the clock supplied on FCLK. Defaults to
32768 Hz.
Default value: Legal values: |
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Fine-tune trim for the internal slow oscillator (CLK_FINE_TUNE, 5-bit
two's-complement code, 0.2% per LSB). Defaults to 0 (no shift).
Default value: Value range: |
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PLL feedback multiplier M, programmed into MDIV as M = MDIV + 1. Choose M
so PLL_CLK = M x REF_CLK lands in 14-28 MHz. Defaults to 444 (the MDIV
reset value of 443).
Default value: Value range: |
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BioZ ADC clock divider (NDIV), dividing PLL_CLK to derive the BioZ ADC
sample clock. Defaults to 512 (the NDIV reset value).
Default value: Legal values: |
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BioZ frequency-synthesis clock divider (KDIV), dividing PLL_CLK to derive
the DDS DAC clock. Defaults to 1 (the KDIV reset value).
Default value: Legal values: |
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BioZ ADC oversampling ratio (BIOZ_ADC_OSR) for the I and Q ADCs. Defaults
to 8 (the reset value).
Default value: Legal values: |
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BioZ DDS DAC oversampling ratio (BIOZ_DAC_OSR). Defaults to 32 (the reset
value).
Default value: Legal values: |
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Enable the in-phase (I) BioZ drive and receive channel (BIOZ_I_EN). Also
turns on the PLL and bandgap bias. Disabled at reset (channel off when
this property is omitted).
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Enable the quadrature-phase (Q) BioZ drive and receive channel
(BIOZ_Q_EN). Also turns on the PLL and bandgap bias. Disabled at reset
(channel off when this property is omitted).
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Enable the BioZ bandgap bias. Disabled
at reset (channel off when this property is omitted).
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BioZ digital high-pass filter cutoff (BIOZ_DHPF[1:0]), expressed as a
register code with the cutoff given relative to the BioZ sample rate.
Defaults to 0 (bypass, the reset value).
Default value: Legal values: |
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BioZ digital low-pass filter cutoff (BIOZ_DLPF[2:0]), expressed as a
register code with the cutoff given relative to the BioZ sample rate.
Defaults to 0 (bypass, the reset value).
Default value: Legal values: |
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Enable the BioZ threshold detector (EN_BIOZ_THRESH), comparing the
bioz-cmp-selected data against bioz-high-threshold and bioz-low-threshold.
Disabled at reset.
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BioZ comparator selection (BIOZ_CMP[1:0]). 0=I, 1=Q, 2=Z. Defaults to 0 (I channel).
Default value: Legal values: |
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Stimulus type driven onto the electrodes by the BioZ transmit channel
(BIOZ_DRV_MODE[1:0]). Defaults to 0 (current drive, the reset value).
Default value: Legal values: |
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Internal current-range resistor (BIOZ_IDRV_RGE), setting the current
magnitude when bioz-ext-res is disabled.
Default value: Legal values: |
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In voltage drive mode, BIOZ_VDRV_MAG sets the voltage amplitude at DRVR,
which is connected to EL1. BIOZ_IDRV_RGE is ignored. In current drive mode,
BIOZ_VDRV_MAG and BIOZ_IDRV_RGE set the current magnitude.
Default value: Legal values: |
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Enable external resistor (REXT) for BioZ current magnitude setting. When
disabled (0), internal range resistors set by BIOZ_IDRV_RGE and BIOZ_VDRV_MAG
are used. When enabled (1), REXT and BIOZ_VDRV_MAG set the current magnitude.
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LOFF_RAPID bypasses the approximately 128ms window delay for DC lead-off detection.
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BIOZ_FAST_START_EN enables the fast-start mode, which connects
the BIP and BIN inputs to VMID_RX through 10kΩ resistors after enabling the I or Q channel.
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BIOZ_FAST_MANUAL is used to turn on the fast-start mode manually.
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BioZ analog high-pass filter cutoff (BIOZ_AHPF[1:0]), expressed as a
register code with the cutoff given relative to the BioZ sample rate.
Defaults to 0 (bypass, the reset value).
Default value: Legal values: |
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BioZ INA mode (BIOZ_INA_MODE) configures the instrumentation amplifier
for either high power (low noise) or low power operation.
Defaults to 0 (high power mode, the reset value).
Default value: Legal values: |
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BIOZ_DM_DIS disables the receive channel demodulators.
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BIOZ_GAIN set the combined gain of the BioZ receive channel's INA and PGAs.
Defaults to 0 (1x gain, the reset value).
Default value: Legal values: |
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BIOZ_EXT_CAP selects the external capacitor (CEXT) connected between
the DRVXC and DRVSJ.
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BIOZ_DC_RESTORE controls the DC restore switch in the current-generator.
Default value: Legal values: |
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Selects the output stage option for the voltage-drive amplifier
and current-drive amplifier within the BioZ transmit channel.
Default value: Legal values: |
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BIOZ_AMP_BW sets the gain bandwidth of the BioZ transmit channel's
voltage-drive and current-drive amplifiers. Defaults to 0 (low bandwidth).
Default value: Legal values: |
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BioZ under-range threshold (BIOZ_LO_THRESH[7:0], 8-bit register code),
compared against the symmetric band +/-32 x code. Only active when
en-bioz-thresh is set. Defaults to 0 (the reset value).
Default value: Value range: |
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BioZ over-range threshold (BIOZ_HI_THRESH[7:0], 8-bit register code),
compared against the symmetric band +/-2048 x code. Only active when
en-bioz-thresh is set. Defaults to 255 (the reset value).
Default value: Value range: |
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BIOZ_STBY_ON keeps the receive channel's amplifiers, demodulators, and ADCs
enabled while the transmit channel is in standby (bioz-drv-mode = 3),
allowing faster wake-up. Disabled at reset.
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BIOZ_Q_CLK_PHASE sets the Q channel demodulator clock phase relative to the
stimulus. 0 = quadrature phase (normal); 1 = in phase. Defaults to 0 (the
reset value).
Default value: Legal values: |
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BIOZ_I_CLK_PHASE sets the I channel demodulator clock phase relative to the
stimulus. 0 = in phase (normal); 1 = quadrature phase. Defaults to 0 (the
reset value).
Default value: Legal values: |
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BIOZ_INA_CHOP_EN enables chopping in the BioZ receive channel's
instrumentation amplifier; the chopping frequency is BIOZ_ADC_CLK / 2. INA
chopping is recommended except when F_BIOZ = BIOZ_ADC_CLK / 2. Disabled at
reset.
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BIOZ_CH_FSEL selects the BioZ receive PGA/AAF chopping frequency: disabled
(0) is BIOZ_ADC_CLK / 8, enabled (1) is BIOZ_ADC_CLK / 4. Set to 1 when
F_BIOZ = BIOZ_ADC_CLK / 8. Disabled at reset.
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BMUX_RSEL selects the resistive calibration load across DRVP/BIP and
DRVN/BIN for non-GSR applications (BMUX_RSEL[1:0]), applied only when
bmux-bist-en is set. Defaults to 0 (5100 ohm, the reset value).
Default value: Legal values: |
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BMUX_BIST_EN connects the built-in self-test resistor (value from
bmux-rsel) between DRVP/BIP and DRVN/BIN for non-GSR applications. Disabled
at reset.
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CONNECT_CAL_ONLY, when set with mux-en and cal-en, connects only the
CAL1-CAL4 pins and disconnects the ELx pins. Disabled at reset.
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MUX_EN enables the BioZ input/output MUX connections to the ELx and/or CALx
pins. When disabled all ELx and CALx pins are disconnected. Disabled at
reset.
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CAL_EN connects the calibration pins (CAL1=DRVP, CAL2=BIP, CAL3=BIN,
CAL4=DRVN) to measure the external calibration resistor when mux-en is set,
disconnecting the electrode pins. Disabled at reset.
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BMUX_GSR_RSEL selects the resistive calibration load across DRVP/BIP and
DRVN/BIN for GSR applications (BMUX_GSR_RSEL[1:0]), applied only when
gsr-load-en is set. Defaults to 0 (25.7 kohm, the reset value).
Default value: Legal values: |
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GSR_LOAD_EN connects the built-in GSR load resistor (value from
bmux-gsr-rsel) between DRVP/BIP and DRVN/BIN. Disabled at reset.
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EN_EXT_INLOAD enables the external guard-trace-drive circuit, which outputs
the buffered voltage from BIP and BIN onto the EL2A and EL3A pins. Disabled
at reset.
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EN_INT_INLOAD enables the circuit that compensates for input capacitive
loading on BIN and BIP. Disabled at reset.
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BIP_ASSIGN selects the electrode pin for the BioZ positive input (BIP) when
mux-en is set (BIP_ASSIGN[1:0]); ignored when cal-en is set. Defaults to 0
(EL1, the reset value).
Default value: Legal values: |
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BIN_ASSIGN selects the electrode pin for the BioZ negative input (BIN) when
mux-en is set (BIN_ASSIGN[1:0]); ignored when cal-en is set. Defaults to 0
(EL4, the reset value).
Default value: Legal values: |
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DRVP_ASSIGN selects the electrode pin for the BioZ positive drive (DRVP) in
current mode when mux-en is set (DRVP_ASSIGN[1:0]); ignored when cal-en is
set, and forced to EL1 in voltage or H-bridge mode. EL1 has the lowest
on-resistance; assign DRVP to EL1 for currents of 64 uA or greater. Defaults
to 0 (EL1, the reset value).
Default value: Legal values: |
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DRVN_ASSIGN selects the electrode pin for the BioZ negative drive (DRVN) in
current mode when mux-en is set (DRVN_ASSIGN[1:0]); ignored when cal-en is
set, and forced to EL4 in voltage or H-bridge mode. EL4 has the lowest
on-resistance; assign DRVN to EL4 for currents of 64 uA or greater. Defaults
to 0 (EL4, the reset value).
Default value: Legal values: |
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EN_LON_DET enables ultra-low-power DC lead-on detection on BIP and BIN. Only
functions when BioZ is disabled (bioz-i-en = bioz-q-en = 0). Disabled at
reset.
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EN_LOFF_DET enables DC lead-off detection on BIP and BIN. Only functions
when BioZ is enabled (bioz-i-en or bioz-q-en set). Disabled at reset.
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EN_EXT_LOFF applies DC lead-off detection externally through EL2B and EL3B
for AC-coupled BioZ inputs on EL2A/EL3A, instead of the internal BIP/BIN
nodes. Disabled at reset.
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EN_DRV_OOR enables the DRVN voltage monitor that detects drive-electrode
lead-off via an out-of-range AC voltage (DRV_OOR status). Disabled at reset.
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LOFF_IPOL sets the polarity of the matched DC lead-off current sources.
Defaults to 0 (non-inverted, the reset value).
Default value: Legal values: |
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LOFF_IMAG selects the DC lead-off current amplitude (LOFF_IMAG[2:0]).
Defaults to 0 (current sources disabled, the reset value).
Default value: Legal values: |
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LOFF_THRESH selects the DC lead-off comparator voltage threshold around
VMID_RX (LOFF_THRESH[3:0], 4-bit code from VMID_RX +/-215 mV at 0 to
+/-665 mV at 15, 30 mV per step). Defaults to 0 (the reset value).
Default value: Value range: |
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RBIAS_VALUE selects the BioZ input lead bias resistance between BIP/BIN and
VMID_RX (RBIAS_VALUE[1:0]), applied when en-rbias-bip or en-rbias-bin is
set. Defaults to 0 (50 Mohm, the reset value).
Default value: Legal values: |
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EN_RBIAS_BIP connects BIP to VMID_RX through the resistor selected by
rbias-value. Disabled at reset.
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EN_RBIAS_BIN connects BIN to VMID_RX through the resistor selected by
rbias-value. Disabled at reset.
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Human readable string describing the sensor. It can be used to
distinguish multiple instances of the same model (e.g., lid accelerometer
vs. base accelerometer in a laptop) to a host operating system.
This property is defined in the Generic Sensor Property Usages of the HID
Usage Tables specification
(https://usb.org/sites/default/files/hut1_3_0.pdf, section 22.5).
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Deprecated node specific properties
Deprecated properties not inherited from the base binding file.
(None)
Base properties
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “adi,max30009” compatible.
Name |
Type |
Details |
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Information used to address the device. The value is specific to
the device (i.e. is different depending on the compatible
property).
The "reg" property is typically a sequence of (address, length) pairs.
Each pair is called a "register block". Values are
conventionally written in hex.
For details, see "2.3.6 reg" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
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Indicates the operational status of the hardware or other
resource that the node represents. In particular:
- "okay" means the resource is operational and, for example,
can be used by device drivers
- "disabled" means the resource is not operational and the system
should treat it as if it is not present
For details, see "2.3.4 status" in Devicetree Specification v0.4.
Legal values: See Important properties for more information. |
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This property is a list of strings that essentially define what
type of hardware or other resource this devicetree node
represents. Each device driver checks for specific compatible
property values to find the devicetree nodes that represent
resources that the driver should manage.
The recommended format is "vendor,device", The "vendor" part is
an abbreviated name of the vendor. The "device" is usually from
the datasheet.
The compatible property can have multiple values, ordered from
most- to least-specific. Having additional values is useful when the
device is a specific instance of a more general family, to allow the
system to match the most specific driver available.
For details, see "2.3.1 compatible" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
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Optional names given to each register block in the "reg" property.
For example:
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
uart@1000 {
reg = <0x1000 0x2000>, <0x3000 0x4000>;
reg-names = "foo", "bar";
};
};
};
The uart@1000 node has two register blocks:
- one with base address 0x1000, size 0x2000, and name "foo"
- another with base address 0x3000, size 0x4000, and name "bar"
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Information used to define a mapping (or translation) between the address
space of a bus (the "child address space") and the address space of the
bus node's parent (the "parent address space").
The "ranges" property is typically empty, or a sequence of triplets
(child bus address, parent bus address, length).
If the "ranges" property is empty, it specifies that the parent and child
address spaces are identical and no address translation is required.
If the "ranges" property is not present in a bus node, it is assumed that
no mapping exists between children of the node and the parent address space.
For details, see "2.3.8 ranges" in Devicetree Specification v0.4.
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Information about interrupts generated by the device, encoded as an array
of one or more interrupt specifiers. The format of the data in this property
varies by where the device appears in the interrupt tree. Devices with the same
"interrupt-parent" will use the same format in their interrupts properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
See Important properties for more information. |
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Extended interrupt specifier for device, used as an alternative to
the "interrupts" property.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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Optional names given to each interrupt generated by a device.
The interrupts themselves are defined in either "interrupts" or
"interrupts-extended" properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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If present, this refers to the node which handles interrupts generated
by this device.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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Human readable string describing the device. Use of this property is
deprecated except as needed on a case-by-case basis.
For details, see "4.1.2 Miscellaneous Properties" in Devicetree
Specification v0.4.
See Important properties for more information. |
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Information about the device's clock providers. In general, this property
should follow conventions established in the dt-schema binding:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml
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Optional names given to each clock provider in the "clocks" property.
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This property encodes the number of <u32> cells used by address fields
in "reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
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This property encodes the number of <u32> cells used by size fields in
"reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
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Indicates that the device is capable of coherent DMA operations.
For details, see "2.3.10 dma-coherent" in Devicetree Specification v0.4.
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DMA channel specifiers relevant to the device.
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Optional names given to the DMA channel specifiers in the "dmas" property.
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IO channel specifiers relevant to the device.
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Optional names given to the IO channel specifiers in the "io-channels" property.
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Mailbox / IPM channel specifiers relevant to the device.
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Optional names given to the mbox specifiers in the "mboxes" property.
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Power domain specifiers relevant to the device.
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Optional names given to the power domain specifiers in the "power-domains" property.
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Number of cells in power-domains property
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HW spinlock id relevant to the device.
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Optional names given to the hwlock specifiers in the "hwlocks" property.
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Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
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Automatically configure the device for runtime power management after the
init function runs.
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List of power states that will disable this device power.
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