intel,penwell-spi

Vendor: Intel Corporation

Description

These nodes are “spi” bus nodes.

Intel Penwell SPI

Properties

Properties not inherited from the base binding file.

Name

Type

Details

clock-frequency

int

 
Clock frequency the SPI peripheral is being driven at, in Hz.

cs-gpios

phandle-array

 
An array of chip select GPIOs to use. Each element
in the array specifies a GPIO. The index in the array
corresponds to the child node that the CS gpio controls.

Example:

  spi@... {
          cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
                        <&gpio1 10 GPIO_ACTIVE_LOW>,
                        ...;

          spi-device@0 {
                  reg = <0>;
                  ...
          };
          spi-device@1 {
                  reg = <1>;
                  ...
          };
          ...
  };

The child node "spi-device@0" specifies a SPI device with
chip select controller gpio0, pin 23, and devicetree
GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
devices can be configured in the same way.

If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
intervening hardware inverts the signal to the peripheral device or
the line itself is active high.

If this property is not defined, no chip select GPIOs are set.
SPI controllers with dedicated CS pins do not need to define
the cs-gpios property.

This property is required.

vendor-id

int

 
Vendor ID of the device

device-id

int

 
Device ID of the device

class-rev

int

 
Optional class/revision register filter

class-rev-mask

int

 
Class/revision register mask

pw,cs-mode

int

 
Chip select configuration. possible values:
0: Hardware
1: Software
2: GPIO

This property is required.

pw,cs-output

int

 
Use GSPI chip select CS0 or CS1. GSPI 0, 1 & 2 instance supports both chip selects.
It can be configured with this DTS property. By default, CS0 is set.
Chip select output possible values:
0: CS0
1: CS1

This property is required.

pw,fifo-depth

int

 
SPI controller with embedded Tx and Rx FIFOs.

This property is required.