microchip,xec-qmspi-ldma
Vendor: Microchip Technology Inc.
Note
An implementation of a driver matching this compatible is available in drivers/spi/spi_xec_qmspi_ldma.c.
Description
These nodes are “spi” bus nodes.
Microchip XEC QMSPI controller with local DMA
Properties
Node specific properties
Properties not inherited from the base binding file.
Name |
Type |
Details |
|---|---|---|
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An array of integers encoding each interrupt signal connection.
This information includes the aggregated GIRQ number, GIRQ bit
position, aggregated GIRQ NVIC connection, and direct NVIC
connection of the GIRQ bit.
This property is required. |
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Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.
This property is required. |
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Names for the provided states. The number of names needs to match the
number of states.
This property is required. |
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QMSPI data lines 1, 2, or 4. 1 data line is full-duplex
MOSI and MISO or half-duplex on MOSI only. Lines set to 2
or 4 indicate dual or quad I/O modes.
Defaults to 1 for full duplex driver's support for full-duplex spi.
Legal values: |
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Use QMSPI CS0# or CS1#. Port 0 supports both chip selects.
Ports 1 and 2 implement CS0# only. Defaults to CS0#.
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Delay in QMSPI main clocks from CS# assertion to first clock edge.
If not present use hardware default value. Refer to chip documentation
for QMSPI input clock frequency.
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Delay in QMSPI main clocks from last clock edge to CS# de-assertion.
If not present use hardware default value. Refer to chip documentation
for QMSPI input clock frequency.
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Delay in QMSPI main clocks from CS# de-assertion to driving HOLD#
and WP#. If not present use hardware default value. Refer to chip
documentation for QMSPI input clock frequency.
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Delay in QMSPI main clocks from CS# de-assertion to CS# assertion.
If not present use hardware default value. Refer to chip documentation
for QMSPI input clock frequency.
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Allows different frequencies for CS#0 and CS1# devices. This applies
to ports implementing CS1#.
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An optional signed 8-bit value for adjusting the QMSPI control signal
timing tap.
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An optional signed 8-bit value for adjusting the QMSPI clock signal
timing tap.
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Clock frequency the SPI peripheral is being driven at, in Hz.
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An array of chip select GPIOs to use. Each element
in the array specifies a GPIO. The index in the array
corresponds to the child node that the CS gpio controls.
Example:
spi@... {
cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
<&gpio1 10 GPIO_ACTIVE_LOW>,
...;
spi-device@0 {
reg = <0>;
...
};
spi-device@1 {
reg = <1>;
...
};
...
};
The child node "spi-device@0" specifies a SPI device with
chip select controller gpio0, pin 23, and devicetree
GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
devices can be configured in the same way.
If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
intervening hardware inverts the signal to the peripheral device or
the line itself is active high.
If this property is not defined, no chip select GPIOs are set.
SPI controllers with dedicated CS pins do not need to define
the cs-gpios property.
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The overrun character (ORC) is used when all bytes from the TX buffer
are sent, but the transfer continues due to RX.
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Pin configuration/s for the second state. See pinctrl-0.
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Pin configuration/s for the third state. See pinctrl-0.
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Pin configuration/s for the fourth state. See pinctrl-0.
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Pin configuration/s for the fifth state. See pinctrl-0.
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Deprecated node specific properties
Deprecated properties not inherited from the base binding file.
(None)
Base properties
Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “microchip,xec-qmspi-ldma” compatible.
Name |
Type |
Details |
|---|---|---|
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register space
This property is required. See Important properties for more information. |
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Clock gate information
This property is required. |
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interrupts for device
This property is required. See Important properties for more information. |
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number of address cells in reg property
This property is required. Constant value: |
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number of size cells in reg property
This property is required. |
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indicates the operational status of a device
Legal values: See Important properties for more information. |
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compatible strings
This property is required. See Important properties for more information. |
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name of each register space
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extended interrupt specifier for device
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name of each interrupt
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phandle to interrupt controller node
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Human readable string describing the device (used as device_get_binding() argument)
See Important properties for more information. This property is deprecated. |
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name of each clock
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DMA channels specifiers
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Provided names of DMA channel specifiers
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IO channels specifiers
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Provided names of IO channel specifiers
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mailbox / IPM channels specifiers
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Provided names of mailbox / IPM channel specifiers
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Power domain specifiers
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Provided names of power domain specifiers
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Number of cells in power-domains property
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Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
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Automatically configure the device for runtime power management after the
init function runs.
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List of power states that will disable this device power.
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