nxp,kinetis-dspi

Vendor: NXP Semiconductors N.V.

Description

These nodes are “spi” bus nodes.

NXP Kinetis DSPI controller

Properties

Properties not inherited from the base binding file.

Name

Type

Details

clock-frequency

int

 
Clock frequency the SPI peripheral is being driven at, in Hz.

cs-gpios

phandle-array

 
An array of chip select GPIOs to use. Each element
in the array specifies a GPIO. The index in the array
corresponds to the child node that the CS gpio controls.

Example:

  spi@... {
          cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
                        <&gpio1 10 GPIO_ACTIVE_LOW>,
                        ...;

          spi-device@0 {
                  reg = <0>;
                  ...
          };
          spi-device@1 {
                  reg = <1>;
                  ...
          };
          ...
  };

The child node "spi-device@0" specifies a SPI device with
chip select controller gpio0, pin 23, and devicetree
GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
devices can be configured in the same way.

If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
intervening hardware inverts the signal to the peripheral device or
the line itself is active high.

If this property is not defined, no chip select GPIOs are set.
SPI controllers with dedicated CS pins do not need to define
the cs-gpios property.

pinctrl-0

phandles

 
Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

This property is required.

pinctrl-1

phandles

 
Pin configuration/s for the second state. See pinctrl-0.

pinctrl-2

phandles

 
Pin configuration/s for the third state. See pinctrl-0.

pinctrl-3

phandles

 
Pin configuration/s for the fourth state. See pinctrl-0.

pinctrl-4

phandles

 
Pin configuration/s for the fifth state. See pinctrl-0.

pinctrl-names

string-array

 
Names for the provided states. The number of names needs to match the
number of states.

pcs-sck-delay

int

 
Delay in nanoseconds from the chip select assert to the first clock
edge. If not set, the minimum supported delay is used.

sck-pcs-delay

int

 
Delay in nanoseconds from the last clock edge to the chip select
deassert. If not set, the minimum supported delay is used.

transfer-delay

int

 
Delay in nanoseconds from the chip select deassert to the next chip
select assert. If not set, the minimum supported delay is used.

nxp,rx-tx-chn-share

boolean

 
If the edma channel shared with tx and rx

ctar

int

 
ctar register selection range form 0-1 for master mode, 0 for slave mode

sample-point

int

 
Controls when the DSPI master samples SIN in the Modified Transfer Format.
This field is valid only when the CPHA bit in the CTAR register is 0.

continuous-sck

boolean

 
continuous SCK enable. Note that the continuous SCK is only
supported for CPHA = 1.

rx-fifo-overwrite

boolean

 
receive FIFO overflow overwrite enable. If ROOE = 0, the incoming
data is ignored and the data from the transfer that generated the overflow
is also ignored. If ROOE = 1, the incoming data is shifted to the
shift register.

modified-timing-format

boolean

 
Enables a modified transfer format to be used if true.

tx-fifo-size

int

 
tx fifo size

rx-fifo-size

int

 
rx fifo size