snps,designware-spi

Vendor: Synopsys, Inc.

Description

These nodes are “spi” bus nodes.

Synopsys DesignWare SPI node

Properties

Properties not inherited from the base binding file.

Name

Type

Details

clock-frequency

int

 
Clock frequency the SPI peripheral is being driven at, in Hz.

cs-gpios

phandle-array

 
An array of chip select GPIOs to use. Each element
in the array specifies a GPIO. The index in the array
corresponds to the child node that the CS gpio controls.

Example:

  spi@... {
          cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
                        <&gpio1 10 GPIO_ACTIVE_LOW>,
                        ...;

          spi-device@0 {
                  reg = <0>;
                  ...
          };
          spi-device@1 {
                  reg = <1>;
                  ...
          };
          ...
  };

The child node "spi-device@0" specifies a SPI device with
chip select controller gpio0, pin 23, and devicetree
GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
devices can be configured in the same way.

If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
intervening hardware inverts the signal to the peripheral device or
the line itself is active high.

If this property is not defined, no chip select GPIOs are set.
SPI controllers with dedicated CS pins do not need to define
the cs-gpios property.

pinctrl-0

phandles

 
Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.

pinctrl-1

phandles

 
Pin configuration/s for the second state. See pinctrl-0.

pinctrl-2

phandles

 
Pin configuration/s for the third state. See pinctrl-0.

pinctrl-3

phandles

 
Pin configuration/s for the fourth state. See pinctrl-0.

pinctrl-4

phandles

 
Pin configuration/s for the fifth state. See pinctrl-0.

pinctrl-names

string-array

 
Names for the provided states. The number of names needs to match the
number of states.

aux-reg

boolean

 
This value is used for auxiliary register access. For
other platform, this value should be default 0.

fifo-depth

int

 
RX/TX FIFO depth. Corresponds to the SSI_TX_FIFO_DEPTH
and SSI_RX_FIFO_DEPTH of the DesignWare Synchronous
Serial Interface. Depth ranges from 2-256.

serial-target

boolean

 
True if it is a Serial Target. False if it is a Serial
Master. Corresponds to SSI_IS_MASTER of the Designware
Synchronous Serial Interface.

max-xfer-size

int

 
Maximum transfer size. Corresponds to SPI_MAX_XFER_SIZE
of the DesignWare Synchronous Serial Interface. Only
values of 16 and 32 are supported.

Legal values: 16, 32