adi-max32-hpb.h

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/*
 * Copyright 2023 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_ADI_MAX32_HPB_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_ADI_MAX32_HPB_H_
 
#define ADI_MAX32_HPB_CS_HIGH_1_5  0  
#define ADI_MAX32_HPB_CS_HIGH_2_5  1  
#define ADI_MAX32_HPB_CS_HIGH_3_5  2  
#define ADI_MAX32_HPB_CS_HIGH_4_5  3  
#define ADI_MAX32_HPB_CS_HIGH_5_5  4  
#define ADI_MAX32_HPB_CS_HIGH_6_5  5  
#define ADI_MAX32_HPB_CS_HIGH_7_5  6  
#define ADI_MAX32_HPB_CS_HIGH_8_5  7  
#define ADI_MAX32_HPB_CS_HIGH_9_5  8  
#define ADI_MAX32_HPB_CS_HIGH_10_5 9  
#define ADI_MAX32_HPB_CS_HIGH_11_5 10 
#define ADI_MAX32_HPB_CS_HIGH_12_5 11 
#define ADI_MAX32_HPB_CS_HIGH_13_5 12 
#define ADI_MAX32_HPB_CS_HIGH_14_5 13 
#define ADI_MAX32_HPB_CS_HIGH_15_5 14 
#define ADI_MAX32_HPB_CS_HIGH_16_5 15 
#define ADI_MAX32_HPB_CS_SETUP_HOLD_1  0  
#define ADI_MAX32_HPB_CS_SETUP_HOLD_2  1  
#define ADI_MAX32_HPB_CS_SETUP_HOLD_3  2  
#define ADI_MAX32_HPB_CS_SETUP_HOLD_4  3  
#define ADI_MAX32_HPB_CS_SETUP_HOLD_5  4  
#define ADI_MAX32_HPB_CS_SETUP_HOLD_6  5  
#define ADI_MAX32_HPB_CS_SETUP_HOLD_7  6  
#define ADI_MAX32_HPB_CS_SETUP_HOLD_8  7  
#define ADI_MAX32_HPB_CS_SETUP_HOLD_9  8  
#define ADI_MAX32_HPB_CS_SETUP_HOLD_10 9  
#define ADI_MAX32_HPB_CS_SETUP_HOLD_11 10 
#define ADI_MAX32_HPB_CS_SETUP_HOLD_12 11 
#define ADI_MAX32_HPB_CS_SETUP_HOLD_13 12 
#define ADI_MAX32_HPB_CS_SETUP_HOLD_14 13 
#define ADI_MAX32_HPB_CS_SETUP_HOLD_15 14 
#define ADI_MAX32_HPB_CS_SETUP_HOLD_16 15 
#define ADI_MAX32_HPB_LAT_5 0x0 
#define ADI_MAX32_HPB_LAT_6 0x1 
#define ADI_MAX32_HPB_LAT_3 0xE 
#define ADI_MAX32_HPB_LAT_4 0xF 
#define ADI_MAX32_HPB_DEV_TYPE_HYPER_FLASH  0
#define ADI_MAX32_HPB_DEV_TYPE_XCCELA_PSRAM 1
#define ADI_MAX32_HPB_DEV_TYPE_HYPER_RAM    2
 
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_ADI_MAX32_HPB_H_ */