Zephyr Project API 4.4.99
A Scalable Open Source RTOS
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alif-ensemble-clocks.h
Go to the documentation of this file.
1/*
2 * Copyright (c) 2025 Alif Semiconductor
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ALIF_ENSEMBLE_CLOCKS_H_
8#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ALIF_ENSEMBLE_CLOCKS_H_
9
17
18#include "alif-clocks-common.h"
19
24
26#define ALIF_UART_CTRL_REG 0x08U
27
29#define ALIF_I2C0_CTRL_REG 0x50U
31#define ALIF_I2C1_CTRL_REG 0x54U
33#define ALIF_I2C2_CTRL_REG 0x58U
35#define ALIF_I2C3_CTRL_REG 0x5CU
36
38#define ALIF_TIMER_CLKSEL_REG 0x04U
39
41
46
48#define ALIF_UART0_SYST_PCLK \
49 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 0U, 1U, 1U, 1U, 8U, ALIF_PARENT_CLK_SYST_PCLK)
50
51#define ALIF_UART1_SYST_PCLK \
52 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 1U, 1U, 1U, 1U, 9U, ALIF_PARENT_CLK_SYST_PCLK)
53
54#define ALIF_UART2_SYST_PCLK \
55 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 2U, 1U, 1U, 1U, 10U, ALIF_PARENT_CLK_SYST_PCLK)
56
57#define ALIF_UART3_SYST_PCLK \
58 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 3U, 1U, 1U, 1U, 11U, ALIF_PARENT_CLK_SYST_PCLK)
59
60#define ALIF_UART4_SYST_PCLK \
61 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 4U, 1U, 1U, 1U, 12U, ALIF_PARENT_CLK_SYST_PCLK)
62
63#define ALIF_UART5_SYST_PCLK \
64 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 5U, 1U, 1U, 1U, 13U, ALIF_PARENT_CLK_SYST_PCLK)
65
66#define ALIF_UART6_SYST_PCLK \
67 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 6U, 1U, 1U, 1U, 14U, ALIF_PARENT_CLK_SYST_PCLK)
68
69#define ALIF_UART7_SYST_PCLK \
70 ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 7U, 1U, 1U, 1U, 15U, ALIF_PARENT_CLK_SYST_PCLK)
71
73
78
80#define ALIF_I2C0_SYST_PCLK \
81 ALIF_CLK_CFG(CLKCTL_PER_SLV, I2C0_CTRL, 0U, 1U, 0U, 0U, 0U, ALIF_PARENT_CLK_SYST_PCLK)
82
83#define ALIF_I2C1_SYST_PCLK \
84 ALIF_CLK_CFG(CLKCTL_PER_SLV, I2C1_CTRL, 0U, 1U, 0U, 0U, 0U, ALIF_PARENT_CLK_SYST_PCLK)
85
86#define ALIF_I2C2_SYST_PCLK \
87 ALIF_CLK_CFG(CLKCTL_PER_SLV, I2C2_CTRL, 0U, 1U, 0U, 0U, 0U, ALIF_PARENT_CLK_SYST_PCLK)
88
89#define ALIF_I2C3_SYST_PCLK \
90 ALIF_CLK_CFG(CLKCTL_PER_SLV, I2C3_CTRL, 0U, 1U, 0U, 0U, 0U, ALIF_PARENT_CLK_SYST_PCLK)
91
93
102
104#define ALIF_LPTIMER0_S32K_CLK \
105 ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 0U, 2U, 0U, ALIF_PARENT_CLK_S32K)
106
107#define ALIF_LPTIMER0_128K_CLK \
108 ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 1U, 2U, 0U, ALIF_PARENT_CLK_128K)
109
110#define ALIF_LPTIMER1_S32K_CLK \
111 ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 0U, 2U, 4U, ALIF_PARENT_CLK_S32K)
112
113#define ALIF_LPTIMER1_128K_CLK \
114 ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 1U, 2U, 4U, ALIF_PARENT_CLK_128K)
115
116#define ALIF_LPTIMER2_S32K_CLK \
117 ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 0U, 2U, 8U, ALIF_PARENT_CLK_S32K)
118
119#define ALIF_LPTIMER2_128K_CLK \
120 ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 1U, 2U, 8U, ALIF_PARENT_CLK_128K)
121
122#define ALIF_LPTIMER3_S32K_CLK \
123 ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 0U, 2U, 12U, ALIF_PARENT_CLK_S32K)
124
125#define ALIF_LPTIMER3_128K_CLK \
126 ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 1U, 2U, 12U, ALIF_PARENT_CLK_128K)
127
129
130#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ALIF_ENSEMBLE_CLOCKS_H_ */
alif-clocks-common.h
Common clock definitions for Alif Semiconductor SoC families.