alif-ensemble-clocks.h

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/*
 * Copyright (c) 2025 Alif Semiconductor
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ALIF_ENSEMBLE_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ALIF_ENSEMBLE_CLOCKS_H_

 
#include "alif-clocks-common.h"


#define ALIF_UART_CTRL_REG              0x08U

#define ALIF_I2C0_CTRL_REG              0x50U
#define ALIF_I2C1_CTRL_REG              0x54U
#define ALIF_I2C2_CTRL_REG              0x58U
#define ALIF_I2C3_CTRL_REG              0x5CU

#define ALIF_TIMER_CLKSEL_REG           0x04U



#define ALIF_UART0_SYST_PCLK        \
        ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 0U, 1U, 1U, 1U, 8U, ALIF_PARENT_CLK_SYST_PCLK)

#define ALIF_UART1_SYST_PCLK        \
        ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 1U, 1U, 1U, 1U, 9U, ALIF_PARENT_CLK_SYST_PCLK)

#define ALIF_UART2_SYST_PCLK        \
        ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 2U, 1U, 1U, 1U, 10U, ALIF_PARENT_CLK_SYST_PCLK)

#define ALIF_UART3_SYST_PCLK        \
        ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 3U, 1U, 1U, 1U, 11U, ALIF_PARENT_CLK_SYST_PCLK)

#define ALIF_UART4_SYST_PCLK        \
        ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 4U, 1U, 1U, 1U, 12U, ALIF_PARENT_CLK_SYST_PCLK)

#define ALIF_UART5_SYST_PCLK        \
        ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 5U, 1U, 1U, 1U, 13U, ALIF_PARENT_CLK_SYST_PCLK)

#define ALIF_UART6_SYST_PCLK        \
        ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 6U, 1U, 1U, 1U, 14U, ALIF_PARENT_CLK_SYST_PCLK)

#define ALIF_UART7_SYST_PCLK        \
        ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 7U, 1U, 1U, 1U, 15U, ALIF_PARENT_CLK_SYST_PCLK)



#define ALIF_I2C0_SYST_PCLK         \
        ALIF_CLK_CFG(CLKCTL_PER_SLV, I2C0_CTRL, 0U, 1U, 0U, 0U, 0U, ALIF_PARENT_CLK_SYST_PCLK)

#define ALIF_I2C1_SYST_PCLK         \
        ALIF_CLK_CFG(CLKCTL_PER_SLV, I2C1_CTRL, 0U, 1U, 0U, 0U, 0U, ALIF_PARENT_CLK_SYST_PCLK)

#define ALIF_I2C2_SYST_PCLK         \
        ALIF_CLK_CFG(CLKCTL_PER_SLV, I2C2_CTRL, 0U, 1U, 0U, 0U, 0U, ALIF_PARENT_CLK_SYST_PCLK)

#define ALIF_I2C3_SYST_PCLK         \
        ALIF_CLK_CFG(CLKCTL_PER_SLV, I2C3_CTRL, 0U, 1U, 0U, 0U, 0U, ALIF_PARENT_CLK_SYST_PCLK)



#define ALIF_LPTIMER0_S32K_CLK      \
        ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 0U, 2U, 0U, ALIF_PARENT_CLK_S32K)

#define ALIF_LPTIMER0_128K_CLK      \
        ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 1U, 2U, 0U, ALIF_PARENT_CLK_128K)

#define ALIF_LPTIMER1_S32K_CLK      \
        ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 0U, 2U, 4U, ALIF_PARENT_CLK_S32K)

#define ALIF_LPTIMER1_128K_CLK      \
        ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 1U, 2U, 4U, ALIF_PARENT_CLK_128K)

#define ALIF_LPTIMER2_S32K_CLK      \
        ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 0U, 2U, 8U, ALIF_PARENT_CLK_S32K)

#define ALIF_LPTIMER2_128K_CLK      \
        ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 1U, 2U, 8U, ALIF_PARENT_CLK_128K)

#define ALIF_LPTIMER3_S32K_CLK      \
        ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 0U, 2U, 12U, ALIF_PARENT_CLK_S32K)

#define ALIF_LPTIMER3_128K_CLK      \
        ALIF_CLK_CFG(VBAT, TIMER_CLKSEL, 0U, 0U, 1U, 2U, 12U, ALIF_PARENT_CLK_128K)

 
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ALIF_ENSEMBLE_CLOCKS_H_ */