Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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sys_io.h
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1/*
2 * Copyright (c) 2015 Intel Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_ARCH_ARC_V2_SYS_IO_H_
8#define ZEPHYR_INCLUDE_ARCH_ARC_V2_SYS_IO_H_
9
10#ifndef _ASMLANGUAGE
11
12#include <zephyr/toolchain.h>
13#include <zephyr/sys/sys_io.h>
15
16#include <zephyr/types.h>
17#include <stddef.h>
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23/* Implementation of sys_io.h's documented functions */
24
25static ALWAYS_INLINE
27{
28 z_arc_v2_aux_reg_write(port, data);
29}
30
31static ALWAYS_INLINE
33{
34 return (uint8_t)(z_arc_v2_aux_reg_read(port) & 0x000000ff);
35}
36
37static ALWAYS_INLINE
39{
40 z_arc_v2_aux_reg_write(port, data);
41}
42
43static ALWAYS_INLINE
45{
46 return (uint16_t)(z_arc_v2_aux_reg_read(port) & 0x0000ffff);
47}
48
49static ALWAYS_INLINE
51{
52 z_arc_v2_aux_reg_write(port, data);
53}
54
55static ALWAYS_INLINE
57{
58 return z_arc_v2_aux_reg_read(port);
59}
60
61static ALWAYS_INLINE
62 void sys_io_set_bit(io_port_t port, unsigned int bit)
63{
64 uint32_t reg = 0;
65
66 __asm__ volatile("lr %1, [%0]\n"
67 "bset %1, %1, %2\n"
68 "sr %1, [%0];\n\t"
69 :
70 : "ir" (port),
71 "r" (reg), "ir" (bit)
72 : "memory", "cc");
73}
74
75static ALWAYS_INLINE
76 void sys_io_clear_bit(io_port_t port, unsigned int bit)
77{
78 uint32_t reg = 0;
79
80 __asm__ volatile("lr %1, [%0]\n"
81 "bclr %1, %1, %2\n"
82 "sr %1, [%0];\n\t"
83 :
84 : "ir" (port),
85 "r" (reg), "ir" (bit)
86 : "memory", "cc");
87}
88
89static ALWAYS_INLINE
90 int sys_io_test_bit(io_port_t port, unsigned int bit)
91{
92 uint32_t status = _ARC_V2_STATUS32;
93 uint32_t reg = 0;
95
96 __asm__ volatile("lr %2, [%1]\n"
97 "btst %2, %3\n"
98 "lr %0, [%4];\n\t"
99 : "=r" (ret)
100 : "ir" (port),
101 "r" (reg), "ir" (bit), "i" (status)
102 : "memory", "cc");
103
104 return !(ret & _ARC_V2_STATUS32_Z);
105}
106
107static ALWAYS_INLINE
108 int sys_io_test_and_set_bit(io_port_t port, unsigned int bit)
109{
110 int ret;
111
112 ret = sys_io_test_bit(port, bit);
113 sys_io_set_bit(port, bit);
114
115 return ret;
116}
117
118static ALWAYS_INLINE
119 int sys_io_test_and_clear_bit(io_port_t port, unsigned int bit)
120{
121 int ret;
122
123 ret = sys_io_test_bit(port, bit);
124 sys_io_clear_bit(port, bit);
125
126 return ret;
127}
128
129#ifdef __cplusplus
130}
131#endif
132
133#endif /* _ASMLANGUAGE */
134
135#endif /* ZEPHYR_INCLUDE_ARCH_ARC_V2_SYS_IO_H_ */
static ALWAYS_INLINE int sys_io_test_and_set_bit(io_port_t port, unsigned int bit)
Definition sys_io.h:108
static ALWAYS_INLINE int sys_io_test_bit(io_port_t port, unsigned int bit)
Definition sys_io.h:90
static ALWAYS_INLINE uint8_t sys_in8(io_port_t port)
Definition sys_io.h:32
static ALWAYS_INLINE int sys_io_test_and_clear_bit(io_port_t port, unsigned int bit)
Definition sys_io.h:119
static ALWAYS_INLINE void sys_out8(uint8_t data, io_port_t port)
Definition sys_io.h:26
static ALWAYS_INLINE void sys_io_clear_bit(io_port_t port, unsigned int bit)
Definition sys_io.h:76
static ALWAYS_INLINE void sys_out16(uint16_t data, io_port_t port)
Definition sys_io.h:38
static ALWAYS_INLINE void sys_io_set_bit(io_port_t port, unsigned int bit)
Definition sys_io.h:62
static ALWAYS_INLINE uint16_t sys_in16(io_port_t port)
Definition sys_io.h:44
static ALWAYS_INLINE void sys_out32(uint32_t data, io_port_t port)
Definition sys_io.h:50
static ALWAYS_INLINE uint32_t sys_in32(io_port_t port)
Definition sys_io.h:56
ARCv2 auxiliary registers definitions.
#define ALWAYS_INLINE
Definition common.h:129
static ZTEST_BMEM int ret
Definition main.c:16
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
__UINT8_TYPE__ uint8_t
Definition stdint.h:88
__UINT16_TYPE__ uint16_t
Definition stdint.h:89
uint32_t io_port_t
Definition sys_io.h:19
static fdata_t data[2]
Definition test_fifo_contexts.c:15
Macros to abstract toolchain specific capabilities.