Zephyr Project API 4.2.99
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clock_control_ifx_cat1.h
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1/*
2 * Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <cy_sysclk.h>
9#include <cy_systick.h>
10
11#define IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(block) ((cy_en_divider_types_t)((block) & 0x03))
12
13/* Converts the group/div pair into a unique block number. */
14#define IFX_CAT1_PERIPHERAL_GROUP_ADJUST(group, div) (((group) << 2) | (div))
15
16#define IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(gr) \
17 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_8BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
18 (gr), CY_SYSCLK_DIV_8_BIT), \
19 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_16BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
20 (gr), CY_SYSCLK_DIV_16_BIT), \
21 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_16_5BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
22 (gr), CY_SYSCLK_DIV_16_5_BIT), \
23 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL##gr##_24_5BIT = IFX_CAT1_PERIPHERAL_GROUP_ADJUST( \
24 (gr), CY_SYSCLK_DIV_24_5_BIT)
26enum ifx_cat1_resource {
27 IFX_CAT1_RSC_ADC,
28 IFX_CAT1_RSC_ADCMIC,
29 IFX_CAT1_RSC_BLESS,
30 IFX_CAT1_RSC_CAN,
31 IFX_CAT1_RSC_CLKPATH,
32 IFX_CAT1_RSC_CLOCK,
33 IFX_CAT1_RSC_CRYPTO,
68 CY_SYSCLK_DIV_16_5_BIT,
69 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
70 CY_SYSCLK_DIV_24_5_BIT,
72 IFX_CAT1_CLOCK_BLOCK_IMO,
73 IFX_CAT1_CLOCK_BLOCK_ECO,
74 IFX_CAT1_CLOCK_BLOCK_EXT,
75 IFX_CAT1_CLOCK_BLOCK_ALTHF,
76 IFX_CAT1_CLOCK_BLOCK_ALTLF,
77 IFX_CAT1_CLOCK_BLOCK_ILO,
78#if !(defined(SRSS_HT_VARIANT) && (SRSS_HT_VARIANT > 0))
79 IFX_CAT1_CLOCK_BLOCK_PILO,
80#endif
81
82 IFX_CAT1_CLOCK_BLOCK_WCO,
83 IFX_CAT1_CLOCK_BLOCK_MFO,
85 IFX_CAT1_CLOCK_BLOCK_PATHMUX,
87 IFX_CAT1_CLOCK_BLOCK_FLL,
88#if defined(CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)
89 IFX_CAT1_CLOCK_BLOCK_PLL200,
90 IFX_CAT1_CLOCK_BLOCK_PLL400,
91#else
92 IFX_CAT1_CLOCK_BLOCK_PLL,
93#endif
94
95 IFX_CAT1_CLOCK_BLOCK_LF,
96 IFX_CAT1_CLOCK_BLOCK_MF,
97 IFX_CAT1_CLOCK_BLOCK_HF,
99 IFX_CAT1_CLOCK_BLOCK_PUMP,
100 IFX_CAT1_CLOCK_BLOCK_BAK,
101 IFX_CAT1_CLOCK_BLOCK_TIMER,
102 IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK,
104 IFX_CAT1_CLOCK_BLOCK_FAST,
105 IFX_CAT1_CLOCK_BLOCK_PERI,
106 IFX_CAT1_CLOCK_BLOCK_SLOW,
108#elif defined(COMPONENT_CAT1B)
109
110 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT =
111 CY_SYSCLK_DIV_8_BIT,
112 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
113 CY_SYSCLK_DIV_16_BIT,
114 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
115 CY_SYSCLK_DIV_16_5_BIT,
117 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
118 CY_SYSCLK_DIV_24_5_BIT,
121/* The first four items are here for backwards compatibility with old clock APIs */
122#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 1)
123 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0),
124#endif
125#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 2)
126 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1),
127#endif
128#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 3)
129 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(2),
130#endif
131#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 4)
132 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(3),
133#endif
134#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 5)
135 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(4),
136#endif
137#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 6)
138 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(5),
139#endif
140#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 7)
141 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(6),
142#endif
143#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 8)
144 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(7),
145#endif
146#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 9)
147 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(8),
148#endif
149#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 10)
150 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(9),
151#endif
152#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 11)
153 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(10),
154#endif
155#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 12)
156 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(11),
157#endif
158#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 13)
159 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(12),
160#endif
161#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 14)
162 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(13),
163#endif
164#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 15)
165 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(14),
166#endif
167#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 16)
168 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(15),
169#endif
170
171 IFX_CAT1_CLOCK_BLOCK_IHO,
172 IFX_CAT1_CLOCK_BLOCK_IMO,
173 IFX_CAT1_CLOCK_BLOCK_ECO,
174 IFX_CAT1_CLOCK_BLOCK_EXT,
175 IFX_CAT1_CLOCK_BLOCK_ALTHF,
176 IFX_CAT1_CLOCK_BLOCK_ALTLF,
177 IFX_CAT1_CLOCK_BLOCK_ILO,
178 IFX_CAT1_CLOCK_BLOCK_PILO,
179 IFX_CAT1_CLOCK_BLOCK_WCO,
180 IFX_CAT1_CLOCK_BLOCK_MFO,
182 IFX_CAT1_CLOCK_BLOCK_PATHMUX,
184 IFX_CAT1_CLOCK_BLOCK_FLL,
185 IFX_CAT1_CLOCK_BLOCK_PLL200,
186 IFX_CAT1_CLOCK_BLOCK_PLL400,
187 IFX_CAT1_CLOCK_BLOCK_ECO_PRESCALER,
189 IFX_CAT1_CLOCK_BLOCK_LF,
190 IFX_CAT1_CLOCK_BLOCK_MF,
191 IFX_CAT1_CLOCK_BLOCK_HF,
193 IFX_CAT1_CLOCK_BLOCK_PUMP,
194 IFX_CAT1_CLOCK_BLOCK_BAK,
195 IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK,
196 IFX_CAT1_CLOCK_BLOCK_PERI,
198#elif defined(COMPONENT_CAT1C)
199
200 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_8BIT =
201 CY_SYSCLK_DIV_8_BIT,
202 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16BIT =
203 CY_SYSCLK_DIV_16_BIT,
204 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_16_5BIT =
205 CY_SYSCLK_DIV_16_5_BIT,
207 IFX_CAT1_CLOCK_BLOCK_PERIPHERAL_24_5BIT =
208 CY_SYSCLK_DIV_24_5_BIT,
211/* The first four items are here for backwards compatibility with old clock APIs */
212#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 1)
213 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(0),
214#endif
215#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 2)
216 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(1),
217#endif
218#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 3)
219 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(2),
220#endif
221#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 4)
222 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(3),
223#endif
224#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 5)
225 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(4),
226#endif
227#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 6)
228 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(5),
229#endif
230#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 7)
231 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(6),
232#endif
233#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 8)
234 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(7),
235#endif
236#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 9)
237 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(8),
238#endif
239#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 10)
240 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(9),
241#endif
242#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 11)
243 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(10),
244#endif
245#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 12)
246 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(11),
247#endif
248#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 13)
249 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(12),
250#endif
251#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 14)
252 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(13),
253#endif
254#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 15)
255 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(14),
256#endif
257#if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 16)
258 IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(15),
259#endif
260
261 IFX_CAT1_CLOCK_BLOCK_IMO,
262 IFX_CAT1_CLOCK_BLOCK_ECO,
263 IFX_CAT1_CLOCK_BLOCK_EXT,
264 IFX_CAT1_CLOCK_BLOCK_ILO,
265 IFX_CAT1_CLOCK_BLOCK_WCO,
267 IFX_CAT1_CLOCK_BLOCK_PATHMUX,
269 IFX_CAT1_CLOCK_BLOCK_FLL,
270 IFX_CAT1_CLOCK_BLOCK_PLL200,
271 IFX_CAT1_CLOCK_BLOCK_PLL400,
273 IFX_CAT1_CLOCK_BLOCK_LF,
274 IFX_CAT1_CLOCK_BLOCK_HF,
275 IFX_CAT1_CLOCK_BLOCK_BAK,
276 IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK,
278 IFX_CAT1_CLOCK_BLOCK_PERI,
279 IFX_CAT1_CLOCK_BLOCK_FAST,
280 IFX_CAT1_CLOCK_BLOCK_SLOW,
281 IFX_CAT1_CLOCK_BLOCK_MEM,
282 IFX_CAT1_CLOCK_BLOCK_TIMER,
283#endif
284};
285
286struct ifx_cat1_clock {
287 enum ifx_cat1_clock_block block;
288 uint8_t channel;
289 bool reserved;
290 const void *funcs;
291};
292
293struct ifx_cat1_resource_inst {
294 enum ifx_cat1_resource type; /* !< The resource block type */
295 uint8_t block_num; /* !< The resource block index */
300 uint8_t channel_num;
301};
302
303int ifx_cat1_clock_control_get_frequency(uint32_t dt_ord, uint32_t *frequency);
304
305en_clk_dst_t ifx_cat1_scb_get_clock_index(uint32_t block_num);
306
307static inline cy_rslt_t ifx_cat1_utils_peri_pclk_enable_divider(en_clk_dst_t clk_dest,
308 const struct ifx_cat1_clock *_clock)
309{
310#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C)
311 return Cy_SysClk_PeriPclkEnableDivider(
312 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
313 _clock->channel);
314#else
315 CY_UNUSED_PARAMETER(clk_dest);
316 return Cy_SysClk_PeriphEnableDivider(
317 IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block), _clock->channel);
318#endif
319}
320
321static inline cy_rslt_t ifx_cat1_utils_peri_pclk_set_divider(en_clk_dst_t clk_dest,
322 const struct ifx_cat1_clock *_clock,
323 uint32_t div)
324{
325#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C)
326 return Cy_SysClk_PeriPclkSetDivider(
327 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
328 _clock->channel, div);
329#else
330 CY_UNUSED_PARAMETER(clk_dest);
331 return Cy_SysClk_PeriphSetDivider(IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
332 _clock->channel, div);
333#endif
334}
335
336static inline cy_rslt_t
337ifx_cat1_utils_peri_pclk_set_frac_divider(en_clk_dst_t clk_dest,
338 const struct ifx_cat1_clock *_clock, uint32_t div_int,
339 uint32_t div_frac)
340{
341#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C)
342 return Cy_SysClk_PeriPclkSetFracDivider(
343 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
344 _clock->channel, div_int, div_frac);
345#else
346 CY_UNUSED_PARAMETER(clk_dest);
347 return Cy_SysClk_PeriphSetFracDivider(
348 IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block), _clock->channel, div_int,
349 div_frac);
350#endif
351}
352
353static inline cy_rslt_t ifx_cat1_utils_peri_pclk_assign_divider(en_clk_dst_t clk_dest,
354 const struct ifx_cat1_clock *_clock)
355{
356#if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
357 return Cy_SysClk_PeriPclkAssignDivider(
358 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
359 _clock->channel);
360#else
361 return Cy_SysClk_PeriphAssignDivider(
362 clk_dest, IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(_clock->block),
363 _clock->channel);
364#endif
365}
ifx_cat1_clock_control_get_frequency
int ifx_cat1_clock_control_get_frequency(uint32_t dt_ord, uint32_t *frequency)
IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE
#define IFX_CAT1_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(block)
Definition clock_control_ifx_cat1.h:11
IFX_CAT1_CLOCK_BLOCK_PERI_GROUP
#define IFX_CAT1_CLOCK_BLOCK_PERI_GROUP(gr)
24.5bit Peripheral Divider Group
Definition clock_control_ifx_cat1.h:16
ifx_cat1_resource
ifx_cat1_resource
Definition clock_control_ifx_cat1.h:34
IFX_CAT1_RSC_DW
@ IFX_CAT1_RSC_DW
Datawire DMA controller.
Definition clock_control_ifx_cat1.h:44
IFX_CAT1_RSC_TCPWM
@ IFX_CAT1_RSC_TCPWM
Timer/Counter/PWM block.
Definition clock_control_ifx_cat1.h:62
IFX_CAT1_RSC_CLKPATH
@ IFX_CAT1_RSC_CLKPATH
Clock Path.
Definition clock_control_ifx_cat1.h:39
IFX_CAT1_RSC_ETH
@ IFX_CAT1_RSC_ETH
Ethernet communications block.
Definition clock_control_ifx_cat1.h:45
IFX_CAT1_RSC_INVALID
@ IFX_CAT1_RSC_INVALID
Placeholder for invalid type.
Definition clock_control_ifx_cat1.h:66
IFX_CAT1_RSC_TDM
@ IFX_CAT1_RSC_TDM
TDM block.
Definition clock_control_ifx_cat1.h:63
IFX_CAT1_RSC_SDHC
@ IFX_CAT1_RSC_SDHC
SD Host Controller.
Definition clock_control_ifx_cat1.h:60
IFX_CAT1_RSC_KEYSCAN
@ IFX_CAT1_RSC_KEYSCAN
KeyScan block.
Definition clock_control_ifx_cat1.h:49
IFX_CAT1_RSC_CAN
@ IFX_CAT1_RSC_CAN
CAN communication block.
Definition clock_control_ifx_cat1.h:38
IFX_CAT1_RSC_LCD
@ IFX_CAT1_RSC_LCD
Segment LCD controller.
Definition clock_control_ifx_cat1.h:50
IFX_CAT1_RSC_DMA
@ IFX_CAT1_RSC_DMA
DMA controller.
Definition clock_control_ifx_cat1.h:43
IFX_CAT1_RSC_SDIODEV
@ IFX_CAT1_RSC_SDIODEV
SDIO Device Block.
Definition clock_control_ifx_cat1.h:61
IFX_CAT1_RSC_BLESS
@ IFX_CAT1_RSC_BLESS
Bluetooth communications block.
Definition clock_control_ifx_cat1.h:37
IFX_CAT1_RSC_LPTIMER
@ IFX_CAT1_RSC_LPTIMER
Low power timer.
Definition clock_control_ifx_cat1.h:53
IFX_CAT1_RSC_ADC
@ IFX_CAT1_RSC_ADC
Analog to digital converter.
Definition clock_control_ifx_cat1.h:35
IFX_CAT1_RSC_CRYPTO
@ IFX_CAT1_RSC_CRYPTO
Crypto hardware accelerator.
Definition clock_control_ifx_cat1.h:41
IFX_CAT1_RSC_LIN
@ IFX_CAT1_RSC_LIN
LIN communications block.
Definition clock_control_ifx_cat1.h:51
IFX_CAT1_RSC_UDB
@ IFX_CAT1_RSC_UDB
UDB Array.
Definition clock_control_ifx_cat1.h:64
IFX_CAT1_RSC_LPCOMP
@ IFX_CAT1_RSC_LPCOMP
Low power comparator.
Definition clock_control_ifx_cat1.h:52
IFX_CAT1_RSC_PTC
@ IFX_CAT1_RSC_PTC
Programmable Threshold comparator.
Definition clock_control_ifx_cat1.h:56
IFX_CAT1_RSC_USB
@ IFX_CAT1_RSC_USB
USB communication block.
Definition clock_control_ifx_cat1.h:65
IFX_CAT1_RSC_DAC
@ IFX_CAT1_RSC_DAC
Digital to analog converter.
Definition clock_control_ifx_cat1.h:42
IFX_CAT1_RSC_SMIF
@ IFX_CAT1_RSC_SMIF
Quad-SPI communications block.
Definition clock_control_ifx_cat1.h:57
IFX_CAT1_RSC_OPAMP
@ IFX_CAT1_RSC_OPAMP
Opamp.
Definition clock_control_ifx_cat1.h:54
IFX_CAT1_RSC_SCB
@ IFX_CAT1_RSC_SCB
Serial Communications Block.
Definition clock_control_ifx_cat1.h:59
IFX_CAT1_RSC_RTC
@ IFX_CAT1_RSC_RTC
Real time clock.
Definition clock_control_ifx_cat1.h:58
IFX_CAT1_RSC_ADCMIC
@ IFX_CAT1_RSC_ADCMIC
Analog to digital converter with Analog Mic support.
Definition clock_control_ifx_cat1.h:36
IFX_CAT1_RSC_I2S
@ IFX_CAT1_RSC_I2S
I2S communications block.
Definition clock_control_ifx_cat1.h:47
IFX_CAT1_RSC_GPIO
@ IFX_CAT1_RSC_GPIO
General purpose I/O pin.
Definition clock_control_ifx_cat1.h:46
IFX_CAT1_RSC_CLOCK
@ IFX_CAT1_RSC_CLOCK
Clock.
Definition clock_control_ifx_cat1.h:40
IFX_CAT1_RSC_I3C
@ IFX_CAT1_RSC_I3C
I3C communications block.
Definition clock_control_ifx_cat1.h:48
IFX_CAT1_RSC_PDM
@ IFX_CAT1_RSC_PDM
PCM/PDM communications block.
Definition clock_control_ifx_cat1.h:55
ifx_cat1_scb_get_clock_index
en_clk_dst_t ifx_cat1_scb_get_clock_index(uint32_t block_num)
ifx_cat1_utils_peri_pclk_assign_divider
static cy_rslt_t ifx_cat1_utils_peri_pclk_assign_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *_clock)
Definition clock_control_ifx_cat1.h:361
ifx_cat1_utils_peri_pclk_set_divider
static cy_rslt_t ifx_cat1_utils_peri_pclk_set_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *_clock, uint32_t div)
Definition clock_control_ifx_cat1.h:329
ifx_cat1_clock_block
ifx_cat1_clock_block
Definition clock_control_ifx_cat1.h:69
ifx_cat1_utils_peri_pclk_enable_divider
static cy_rslt_t ifx_cat1_utils_peri_pclk_enable_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *_clock)
Definition clock_control_ifx_cat1.h:315
ifx_cat1_utils_peri_pclk_set_frac_divider
static cy_rslt_t ifx_cat1_utils_peri_pclk_set_frac_divider(en_clk_dst_t clk_dest, const struct ifx_cat1_clock *_clock, uint32_t div_int, uint32_t div_frac)
Definition clock_control_ifx_cat1.h:345
IFX_CAT1_CLOCK_BLOCK_PLL200
#define IFX_CAT1_CLOCK_BLOCK_PLL200
200MHz Phase-Locked Loop Clock
Definition ifx_clock_source_def.h:25
IFX_CAT1_CLOCK_BLOCK_PLL400
#define IFX_CAT1_CLOCK_BLOCK_PLL400
400MHz Phase-Locked Loop Clock
Definition ifx_clock_source_def.h:26
IFX_CAT1_CLOCK_BLOCK_IHO
#define IFX_CAT1_CLOCK_BLOCK_IHO
Internal High Speed Oscillator Input Clock.
Definition ifx_clock_source_def.h:11
IFX_CAT1_CLOCK_BLOCK_ILO
#define IFX_CAT1_CLOCK_BLOCK_ILO
Internal Low Speed Oscillator Input Clock.
Definition ifx_clock_source_def.h:17
IFX_CAT1_CLOCK_BLOCK_ALTLF
#define IFX_CAT1_CLOCK_BLOCK_ALTLF
Alternate Low Frequency Input Clock.
Definition ifx_clock_source_def.h:16
IFX_CAT1_CLOCK_BLOCK_LF
#define IFX_CAT1_CLOCK_BLOCK_LF
Low Frequency Clock.
Definition ifx_clock_source_def.h:29
IFX_CAT1_CLOCK_BLOCK_PERI
#define IFX_CAT1_CLOCK_BLOCK_PERI
Peripheral Clock Group.
Definition ifx_clock_source_def.h:36
IFX_CAT1_CLOCK_BLOCK_EXT
#define IFX_CAT1_CLOCK_BLOCK_EXT
External Input Clock.
Definition ifx_clock_source_def.h:14
IFX_CAT1_CLOCK_BLOCK_FLL
#define IFX_CAT1_CLOCK_BLOCK_FLL
Frequency-Locked Loop Clock.
Definition ifx_clock_source_def.h:24
IFX_CAT1_CLOCK_BLOCK_MF
#define IFX_CAT1_CLOCK_BLOCK_MF
Medium Frequency Clock.
Definition ifx_clock_source_def.h:30
IFX_CAT1_CLOCK_BLOCK_PUMP
#define IFX_CAT1_CLOCK_BLOCK_PUMP
Analog Pump Clock.
Definition ifx_clock_source_def.h:33
IFX_CAT1_CLOCK_BLOCK_ECO_PRESCALER
#define IFX_CAT1_CLOCK_BLOCK_ECO_PRESCALER
ECO Prescaler Divider.
Definition ifx_clock_source_def.h:27
IFX_CAT1_CLOCK_BLOCK_ALTHF
#define IFX_CAT1_CLOCK_BLOCK_ALTHF
Alternate High Frequency Input Clock.
Definition ifx_clock_source_def.h:15
IFX_CAT1_CLOCK_BLOCK_MFO
#define IFX_CAT1_CLOCK_BLOCK_MFO
Medium Frequency Oscillator Clock.
Definition ifx_clock_source_def.h:20
IFX_CAT1_CLOCK_BLOCK_BAK
#define IFX_CAT1_CLOCK_BLOCK_BAK
Backup Power Domain Clock.
Definition ifx_clock_source_def.h:34
IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK
#define IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK
Alternative SysTick Clock.
Definition ifx_clock_source_def.h:35
IFX_CAT1_CLOCK_BLOCK_PILO
#define IFX_CAT1_CLOCK_BLOCK_PILO
Precision ILO Input Clock.
Definition ifx_clock_source_def.h:18
IFX_CAT1_CLOCK_BLOCK_HF
#define IFX_CAT1_CLOCK_BLOCK_HF
High Frequency Clock.
Definition ifx_clock_source_def.h:31
IFX_CAT1_CLOCK_BLOCK_IMO
#define IFX_CAT1_CLOCK_BLOCK_IMO
Internal Main Oscillator Input Clock.
Definition ifx_clock_source_def.h:12
IFX_CAT1_CLOCK_BLOCK_ECO
#define IFX_CAT1_CLOCK_BLOCK_ECO
External Crystal Oscillator Input Clock.
Definition ifx_clock_source_def.h:13
IFX_CAT1_CLOCK_BLOCK_PATHMUX
#define IFX_CAT1_CLOCK_BLOCK_PATHMUX
Path selection mux for input to FLL/PLLs.
Definition ifx_clock_source_def.h:22
IFX_CAT1_CLOCK_BLOCK_WCO
#define IFX_CAT1_CLOCK_BLOCK_WCO
Watch Crystal Oscillator Input Clock.
Definition ifx_clock_source_def.h:19
CY_SYSCLK_DIV_16_BIT
#define CY_SYSCLK_DIV_16_BIT
Definition pwm_ifx_cat1.h:12
CY_SYSCLK_DIV_8_BIT
#define CY_SYSCLK_DIV_8_BIT
Divider Type.
Definition pwm_ifx_cat1.h:11
uint32_t
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
uint8_t
__UINT8_TYPE__ uint8_t
Definition stdint.h:88
ifx_cat1_clock
Definition clock_control_ifx_cat1.h:294
ifx_cat1_clock::funcs
const void * funcs
Definition clock_control_ifx_cat1.h:298
ifx_cat1_clock::channel
uint8_t channel
Definition clock_control_ifx_cat1.h:296
ifx_cat1_clock::block
enum ifx_cat1_clock_block block
Definition clock_control_ifx_cat1.h:295
ifx_cat1_clock::reserved
bool reserved
Definition clock_control_ifx_cat1.h:297
ifx_cat1_resource_inst
Definition clock_control_ifx_cat1.h:301
ifx_cat1_resource_inst::block_num
uint8_t block_num
Definition clock_control_ifx_cat1.h:303
ifx_cat1_resource_inst::channel_num
uint8_t channel_num
The channel number, if the resource type defines multiple channels per block instance.
Definition clock_control_ifx_cat1.h:308
ifx_cat1_resource_inst::type
enum ifx_cat1_resource type
Definition clock_control_ifx_cat1.h:302