Zephyr Project API 4.4.99
A Scalable Open Source RTOS
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clock_control_silabs.h
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1/*
2 * Copyright (c) 2024 Silicon Laboratories Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
12
13#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_SILABS_H_
14#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_SILABS_H_
15
17
23
24#if defined(CONFIG_SOC_FAMILY_SILABS_S2_XG21)
26#elif defined(CONFIG_SOC_FAMILY_SILABS_S2_XG22)
28#elif defined(CONFIG_SOC_FAMILY_SILABS_S2_XG23)
30#elif defined(CONFIG_SOC_FAMILY_SILABS_S2_XG24)
32#elif defined(CONFIG_SOC_FAMILY_SILABS_S2_XG26)
34#elif defined(CONFIG_SOC_FAMILY_SILABS_S2_XG27)
36#elif defined(CONFIG_SOC_FAMILY_SILABS_S2_XG28)
38#elif defined(CONFIG_SOC_FAMILY_SILABS_S2_XG29)
40#elif defined(CONFIG_SOC_FAMILY_SILABS_S3_SIX301)
42#endif
43
49
55#define SILABS_DT_CLOCK_CFG(node_id) \
56 { \
57 .bus_clock = DT_CLOCKS_CELL(node_id, enable), \
58 .branch = DT_CLOCKS_CELL(node_id, branch), \
59 }
60
66#define SILABS_DT_INST_CLOCK_CFG(inst) \
67 { \
68 .bus_clock = DT_INST_CLOCKS_CELL(inst, enable), \
69 .branch = DT_INST_CLOCKS_CELL(inst, branch), \
70 }
71
79#define SILABS_DT_CLOCK_CFG_BY_NAME(node_id, name) \
80 { \
81 .bus_clock = DT_CLOCKS_CELL_BY_NAME(node_id, name, enable), \
82 .branch = DT_CLOCKS_CELL_BY_NAME(node_id, name, branch), \
83 }
84
85
93#define SILABS_DT_INST_CLOCK_CFG_BY_NAME(inst, name) \
94 { \
95 .bus_clock = DT_INST_CLOCKS_CELL_BY_NAME(inst, name, enable), \
96 .branch = DT_INST_CLOCKS_CELL_BY_NAME(inst, name, branch), \
97 }
98
100
101#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_SILABS_H_ */
Main header file for clock control driver API.
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
__UINT8_TYPE__ uint8_t
Definition stdint.h:88
Clock Management Unit (CMU) clock configuration for a peripheral.
Definition clock_control_silabs.h:45
uint32_t bus_clock
Bus clock enable identifier.
Definition clock_control_silabs.h:46
uint8_t branch
Clock branch the peripheral is sourced from.
Definition clock_control_silabs.h:47