Zephyr Project API 3.7.0
A Scalable Open Source RTOS
Loading...
Searching...
No Matches
pcie.h
Go to the documentation of this file.
1/*
2 * Copyright (c) 2019 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PCIE_PCIE_H_
8#define ZEPHYR_INCLUDE_DT_BINDINGS_PCIE_PCIE_H_
9
10/*
11 * Set the device's IRQ (in devicetree, or whatever) to PCIE_IRQ_DETECT
12 * if the device doesn't support MSI and we don't/can't know the wired IRQ
13 * allocated by the firmware ahead of time. Use of this functionality will
14 * generally also require CONFIG_DYNAMIC_INTERRUPTS.
15 */
16
17#define PCIE_IRQ_DETECT 0xFFFFFFFU
18
19/*
20 * We represent a PCI device ID as [31:16] device ID, [15:0] vendor ID. Not
21 * coincidentally, this is same representation used in PCI configuration space.
22 */
23
24#define PCIE_ID_VEND_SHIFT 0U
25#define PCIE_ID_VEND_MASK 0xFFFFU
26#define PCIE_ID_DEV_SHIFT 16U
27#define PCIE_ID_DEV_MASK 0xFFFFU
28
29#ifdef __DTS__
30#define CAST(type, v) (v)
31#else
32#define CAST(type, v) ((type)(v))
33#endif
34
35#define PCIE_ID(vend, dev) \
36 ((((vend) & PCIE_ID_VEND_MASK) << PCIE_ID_VEND_SHIFT) | \
37 (CAST(uint32_t, (dev) & PCIE_ID_DEV_MASK) << PCIE_ID_DEV_SHIFT))
38
39#define PCIE_ID_TO_VEND(id) (((id) >> PCIE_ID_VEND_SHIFT) & PCIE_ID_VEND_MASK)
40#define PCIE_ID_TO_DEV(id) (((id) >> PCIE_ID_DEV_SHIFT) & PCIE_ID_DEV_MASK)
41
42#define PCIE_ID_NONE PCIE_ID(0xFFFF, 0xFFFF)
43
44#define PCIE_BDF_NONE 0xFFFFFFFFU
45
46/*
47 * Since our internal representation of bus/device/function is arbitrary,
48 * we choose the same format employed in the x86 Configuration Address Port:
49 *
50 * [23:16] bus number, [15:11] device number, [10:8] function number
51 *
52 * All other bits must be zero.
53 *
54 * The x86 (the only arch, at present, that supports PCI) takes advantage
55 * of this shared format to avoid unnecessary layers of abstraction.
56 */
57
58#define PCIE_BDF_BUS_SHIFT 16U
59#define PCIE_BDF_BUS_MASK 0xFFU
60#define PCIE_BDF_DEV_SHIFT 11U
61#define PCIE_BDF_DEV_MASK 0x1FU
62#define PCIE_BDF_FUNC_SHIFT 8U
63#define PCIE_BDF_FUNC_MASK 0x7U
64
65#define PCIE_BDF(bus, dev, func) \
66 ((((bus) & PCIE_BDF_BUS_MASK) << PCIE_BDF_BUS_SHIFT) | \
67 (((dev) & PCIE_BDF_DEV_MASK) << PCIE_BDF_DEV_SHIFT) | \
68 (((func) & PCIE_BDF_FUNC_MASK) << PCIE_BDF_FUNC_SHIFT))
69
70#define PCIE_BDF_TO_BUS(bdf) (((bdf) >> PCIE_BDF_BUS_SHIFT) & PCIE_BDF_BUS_MASK)
71#define PCIE_BDF_TO_DEV(bdf) (((bdf) >> PCIE_BDF_DEV_SHIFT) & PCIE_BDF_DEV_MASK)
72
73#define PCIE_BDF_TO_FUNC(bdf) \
74 (((bdf) >> PCIE_BDF_FUNC_SHIFT) & PCIE_BDF_FUNC_MASK)
75
76#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PCIE_PCIE_H_ */