esp-esp32c61-intmux.h

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/*
 * Copyright (c) 2026 Espressif Systems (Shanghai) Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

 
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C61_INTMUX_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C61_INTMUX_H_


 
#define WIFI_MAC_INTR_SOURCE           0  
#define WIFI_MAC_NMI_SOURCE            1  
#define WIFI_PWR_INTR_SOURCE           2  
#define WIFI_BB_INTR_SOURCE            3  
#define BT_MAC_INTR_SOURCE             4  
#define BT_BB_INTR_SOURCE              5  
#define BT_BB_NMI_SOURCE               6  
#define LP_TIMER_INTR_SOURCE           7  
#define COEX_INTR_SOURCE               8  
#define BLE_TIMER_INTR_SOURCE          9  
#define BLE_SEC_INTR_SOURCE            10 
#define I2C_MASTER_SOURCE              11 
#define ZB_MAC_SOURCE                  12 
#define PMU_INTR_SOURCE                13 
#define EFUSE_INTR_SOURCE              14 
#define LP_RTC_TIMER_INTR_SOURCE       15 
#define LP_WDT_INTR_SOURCE             16 
#define LP_PERI_TIMEOUT_INTR_SOURCE    17 
#define LP_APM_M0_INTR_SOURCE          18 
#define FROM_CPU_INTR0_SOURCE          19 
#define FROM_CPU_INTR1_SOURCE          20 
#define FROM_CPU_INTR2_SOURCE          21 
#define FROM_CPU_INTR3_SOURCE          22 
#define ASSIST_DEBUG_INTR_SOURCE       23 
#define TRACE_INTR_SOURCE              24 
#define CACHE_INTR_SOURCE              25 
#define CPU_PERI_TIMEOUT_INTR_SOURCE   26 
#define GPIO_INTR_SOURCE               27 
#define GPIO_EXT_SOURCE                28 
#define PAU_INTR_SOURCE                29 
#define HP_PERI_TIMEOUT_INTR_SOURCE    30 
#define MODEM_PERI_TIMEOUT_INTR_SOURCE 31 
#define HP_APM_M0_INTR_SOURCE          32 
#define HP_APM_M1_INTR_SOURCE          33 
#define HP_APM_M2_INTR_SOURCE          34 
#define HP_APM_M3_INTR_SOURCE          35 
#define CPU_APM_M0_INTR_SOURCE         36 
#define CPU_APM_M1_INTR_SOURCE         37 
#define MSPI_INTR_SOURCE               38 
#define I2S0_INTR_SOURCE               39 
#define UART0_INTR_SOURCE              40 
#define UART1_INTR_SOURCE              41 
#define UART2_INTR_SOURCE              42 
#define LEDC_INTR_SOURCE               43 
#define USB_SERIAL_JTAG_INTR_SOURCE    44 
#define I2C_EXT0_INTR_SOURCE           45 
#define TG0_T0_LEVEL_INTR_SOURCE       46 
#define TG0_T1_LEVEL_INTR_SOURCE       47 
#define TG0_WDT_LEVEL_INTR_SOURCE      48 
#define TG1_T0_LEVEL_INTR_SOURCE       49 
#define TG1_T1_LEVEL_INTR_SOURCE       50 
#define TG1_WDT_LEVEL_INTR_SOURCE      51 
#define SYSTIMER_TARGET0_INTR_SOURCE   52 
#define SYSTIMER_TARGET1_INTR_SOURCE   53 
#define SYSTIMER_TARGET2_INTR_SOURCE   54 
#define APB_ADC_INTR_SOURCE            55 
#define SLC0_INTR_SOURCE               56 
#define SLC1_INTR_SOURCE               57 
#define DMA_IN_CH0_INTR_SOURCE         58 
#define DMA_IN_CH1_INTR_SOURCE         59 
#define DMA_OUT_CH0_INTR_SOURCE        60 
#define DMA_OUT_CH1_INTR_SOURCE        61 
#define GSPI2_INTR_SOURCE              62 
#define SHA_INTR_SOURCE                63 
#define ECC_INTR_SOURCE                64 
#define ECDSA_INTR_SOURCE              65 
#define MAX_INTR_SOURCE                66 

#define IRQ_DEFAULT_PRIORITY 0
 
#define ESP_INTR_FLAG_SHARED (1 << 8) 


 
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C61_INTMUX_H_ */