Zephyr Project API 4.3.99
A Scalable Open Source RTOS
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esp32_clock.h
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1/*
2 * Copyright (c) 2020 Mohamed ElShahawi
3 * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32_H_
9#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32_H_
10
11/* Supported CPU clock Sources */
12#define ESP32_CPU_CLK_SRC_XTAL 0U
13#define ESP32_CPU_CLK_SRC_PLL 1U
14#define ESP32_CLK_SRC_RC_FAST 2U
15#define ESP32_CLK_SRC_APLL_CLK 3U
16
17/* Supported PLL CPU frequencies */
18#define ESP32_CLK_CPU_PLL_80M 80000000
19#define ESP32_CLK_CPU_PLL_160M 160000000
20#define ESP32_CLK_CPU_PLL_240M 240000000
21#define ESP32_CLK_CPU_RC_FAST_FREQ 1062500
22
23/* Supported XTAL frequencies */
24#define ESP32_CLK_XTAL_24M 24000000
25#define ESP32_CLK_XTAL_26M 26000000
26#define ESP32_CLK_XTAL_40M 40000000
27
28/* Supported RTC fast clock sources */
29#define ESP32_RTC_FAST_CLK_SRC_XTAL_D4 0
30#define ESP32_RTC_FAST_CLK_SRC_RC_FAST 1
31
32/* Supported RTC slow clock sources */
33#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0
34#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K 1
35#define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256 2
36#define ESP32_RTC_SLOW_CLK_32K_EXT_OSC 9
37
38/* RTC slow clock frequencies */
39#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 150000
40#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ 32768
41#define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256_FREQ 33203
42
43/* Modules IDs
44 * These are used by the clock control driver to identify peripheral modules.
45 */
46#define ESP32_UART1_MODULE 0
47#define ESP32_UART2_MODULE 1
48#define ESP32_I2S0_MODULE 2
49#define ESP32_TIMG0_MODULE 3
50#define ESP32_TIMG1_MODULE 4
51#define ESP32_UHCI0_MODULE 5
52#define ESP32_SPI_MODULE 6
53#define ESP32_HSPI_MODULE 7
54#define ESP32_VSPI_MODULE 8
55#define ESP32_RNG_MODULE 9
56#define ESP32_WIFI_MODULE 10
57#define ESP32_BT_MODULE 11
58#define ESP32_WIFI_BT_COMMON_MODULE 12
59#define ESP32_BT_BASEBAND_MODULE 13
60#define ESP32_PHY_CALIBRATION_MODULE 14
61#define ESP32_MODULE_MAX 15
62
63/* Non-shared peripherals - these have dedicated clock control in their drivers
64 * and don't use periph_module_enable(). Values start after MODULE_MAX.
65 */
66#define ESP32_LEDC_MODULE 100
67#define ESP32_UART0_MODULE 101
68#define ESP32_I2C0_MODULE 102
69#define ESP32_I2C1_MODULE 103
70#define ESP32_I2S1_MODULE 104
71#define ESP32_PWM0_MODULE 105
72#define ESP32_PWM1_MODULE 106
73#define ESP32_UHCI1_MODULE 107
74#define ESP32_RMT_MODULE 108
75#define ESP32_PCNT_MODULE 109
76#define ESP32_SPI_DMA_MODULE 110
77#define ESP32_SDMMC_MODULE 111
78#define ESP32_SDIO_SLAVE_MODULE 112
79#define ESP32_TWAI_MODULE 113
80#define ESP32_CAN_MODULE ESP32_TWAI_MODULE
81#define ESP32_EMAC_MODULE 114
82#define ESP32_AES_MODULE 115
83#define ESP32_SHA_MODULE 116
84#define ESP32_RSA_MODULE 117
85#define ESP32_SARADC_MODULE 118
86#define ESP32_BT_LC_MODULE 119
87
88#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32_H_ */