Zephyr Project API 4.4.99
A Scalable Open Source RTOS
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gd32c2x1-clocks.h
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1/*
2 * Copyright (c) 2026 GigaDevice Semiconductor Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
11
12#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32C2X1_CLOCKS_H_
13#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32C2X1_CLOCKS_H_
14
15#include "gd32-clocks-common.h"
16
21
22#define GD32_AHB1EN_OFFSET 0x30U
23#define GD32_AHB2EN_OFFSET 0x34U
24#define GD32_APBEN_OFFSET 0x44U
25
27
32
33/* AHB1 peripherals */
34#define GD32_CLOCK_FMC GD32_CLOCK_CONFIG(AHB1EN, 4U)
35#define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHB1EN, 12U)
36#define GD32_CLOCK_DMA GD32_CLOCK_CONFIG(AHB1EN, 21U)
37#define GD32_CLOCK_DMAMUX GD32_CLOCK_CONFIG(AHB1EN, 23U)
38
39/* AHB2 peripherals */
40#define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHB2EN, 17U)
41#define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(AHB2EN, 18U)
42#define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(AHB2EN, 19U)
43#define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(AHB2EN, 20U)
44#define GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(AHB2EN, 22U)
45
46/* APB peripherals */
47#define GD32_CLOCK_SYSCFG GD32_CLOCK_CONFIG(APBEN, 0U)
48#define GD32_CLOCK_CMP GD32_CLOCK_CONFIG(APBEN, 1U)
49#define GD32_CLOCK_WWDGT GD32_CLOCK_CONFIG(APBEN, 8U)
50#define GD32_CLOCK_ADC GD32_CLOCK_CONFIG(APBEN, 9U)
51#define GD32_CLOCK_TIMER0 GD32_CLOCK_CONFIG(APBEN, 10U)
52#define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APBEN, 11U)
53#define GD32_CLOCK_SPI0 GD32_CLOCK_CONFIG(APBEN, 12U)
54#define GD32_CLOCK_SPI1 GD32_CLOCK_CONFIG(APBEN, 13U)
55#define GD32_CLOCK_USART0 GD32_CLOCK_CONFIG(APBEN, 14U)
56#define GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APBEN, 15U)
57#define GD32_CLOCK_TIMER13 GD32_CLOCK_CONFIG(APBEN, 16U)
58#define GD32_CLOCK_TIMER15 GD32_CLOCK_CONFIG(APBEN, 17U)
59#define GD32_CLOCK_TIMER16 GD32_CLOCK_CONFIG(APBEN, 18U)
60#define GD32_CLOCK_USART2 GD32_CLOCK_CONFIG(APBEN, 19U)
61#define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APBEN, 21U)
62#define GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APBEN, 22U)
63#define GD32_CLOCK_DBG GD32_CLOCK_CONFIG(APBEN, 27U)
64#define GD32_CLOCK_PMU GD32_CLOCK_CONFIG(APBEN, 28U)
65
67
68#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32C2X1_CLOCKS_H_ */