gpio_rp1.h

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/*
 * Copyright (c) 2024 Junho Lee <junho@tsnlab.com>
 * Copyright (c) 2025 TOKITA Hiroshi
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 
#ifndef ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_RP1_H
#define ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_RP1_H


 
/* Bit positions and masks for the RP1 GPIO control register. */
#define GPIO_CTRL_FUNCSEL_SHIFT               0
#define GPIO_CTRL_FUNCSEL_MASK                (BIT_MASK(5) << GPIO_CTRL_FUNCSEL_SHIFT)
#define GPIO_CTRL_F_M_SHIFT                   5
#define GPIO_CTRL_F_M_MASK                    (BIT_MASK(7) << GPIO_CTRL_F_M_SHIFT)
#define GPIO_CTRL_OUTOVER_SHIFT               12
#define GPIO_CTRL_OUTOVER_MASK                (BIT_MASK(2) << GPIO_CTRL_OUTOVER_SHIFT)
#define GPIO_CTRL_OEOVER_SHIFT                14
#define GPIO_CTRL_OEOVER_MASK                 (BIT_MASK(2) << GPIO_CTRL_OEOVER_SHIFT)
#define GPIO_CTRL_INOVER_SHIFT                16
#define GPIO_CTRL_INOVER_MASK                 (BIT_MASK(2) << GPIO_CTRL_INOVER_SHIFT)
#define GPIO_CTRL_IRQMASK_EDGE_LOW_SHIFT      20
#define GPIO_CTRL_IRQMASK_EDGE_LOW_MASK       (BIT_MASK(1) << GPIO_CTRL_IRQMASK_EDGE_LOW_SHIFT)
#define GPIO_CTRL_IRQMASK_EDGE_HIGH_SHIFT     21
#define GPIO_CTRL_IRQMASK_EDGE_HIGH_MASK      (BIT_MASK(1) << GPIO_CTRL_IRQMASK_EDGE_HIGH_SHIFT)
#define GPIO_CTRL_IRQMASK_LEVEL_LOW_SHIFT     22
#define GPIO_CTRL_IRQMASK_LEVEL_LOW_MASK      (BIT_MASK(1) << GPIO_CTRL_IRQMASK_LEVEL_LOW_SHIFT)
#define GPIO_CTRL_IRQMASK_LEVEL_HIGH_SHIFT    23
#define GPIO_CTRL_IRQMASK_LEVEL_HIGH_MASK     (BIT_MASK(1) << GPIO_CTRL_IRQMASK_LEVEL_HIGH_SHIFT)
#define GPIO_CTRL_IRQMASK_F_EDGE_LOW_SHIFT    24
#define GPIO_CTRL_IRQMASK_F_EDGE_LOW_MASK     (BIT_MASK(1) << GPIO_CTRL_IRQMASK_F_EDGE_LOW_SHIFT)
#define GPIO_CTRL_IRQMASK_F_EDGE_HIGH_SHIFT   25
#define GPIO_CTRL_IRQMASK_F_EDGE_HIGH_MASK    (BIT_MASK(1) << GPIO_CTRL_IRQMASK_F_EDGE_HIGH_SHIFT)
#define GPIO_CTRL_IRQMASK_DB_LEVEL_LOW_SHIFT  26
#define GPIO_CTRL_IRQMASK_DB_LEVEL_LOW_MASK   (BIT_MASK(1) << GPIO_CTRL_IRQMASK_DB_LEVEL_LOW_SHIFT)
#define GPIO_CTRL_IRQMASK_DB_LEVEL_HIGH_SHIFT 27
#define GPIO_CTRL_IRQMASK_DB_LEVEL_HIGH_MASK  (BIT_MASK(1) << GPIO_CTRL_IRQMASK_DB_LEVEL_HIGH_SHIFT)
#define GPIO_CTRL_IRQRESET_SHIFT              28
#define GPIO_CTRL_IRQRESET_MASK               (BIT_MASK(1) << GPIO_CTRL_IRQRESET_SHIFT)
#define GPIO_CTRL_IRQOVER_SHIFT               30
#define GPIO_CTRL_IRQOVER_MASK                (BIT_MASK(2) << GPIO_CTRL_IRQOVER_SHIFT)
 
/* Reserved bits in the RP1 GPIO control register. */
#define GPIO_CTRL_RESERVED_MASK (BIT(29) | BIT(19) | BIT(18))
 
/* Bit positions and masks for the RP1 pad control register. */
#define GPIO_PADS_SLEWFAST_SHIFT         0
#define GPIO_PADS_SLEWFAST_MASK          (BIT_MASK(1) << GPIO_PADS_SLEWFAST_SHIFT)
#define GPIO_PADS_SCHMITT_ENABLE_SHIFT   1
#define GPIO_PADS_SCHMITT_ENABLE_MASK    (BIT_MASK(1) << GPIO_PADS_SCHMITT_ENABLE_SHIFT)
#define GPIO_PADS_PULL_DOWN_ENABLE_SHIFT 2
#define GPIO_PADS_PULL_DOWN_ENABLE_MASK  (BIT_MASK(1) << GPIO_PADS_PULL_DOWN_ENABLE_SHIFT)
#define GPIO_PADS_PULL_UP_ENABLE_SHIFT   3
#define GPIO_PADS_PULL_UP_ENABLE_MASK    (BIT_MASK(1) << GPIO_PADS_PULL_UP_ENABLE_SHIFT)
#define GPIO_PADS_DRIVE_SHIFT            4
#define GPIO_PADS_DRIVE_MASK             (BIT_MASK(2) << GPIO_PADS_DRIVE_SHIFT)
#define GPIO_PADS_INPUT_ENABLE_SHIFT     6
#define GPIO_PADS_INPUT_ENABLE_MASK      (BIT_MASK(1) << GPIO_PADS_INPUT_ENABLE_SHIFT)
#define GPIO_PADS_OUTPUT_DISABLE_SHIFT   7
#define GPIO_PADS_OUTPUT_DISABLE_MASK    (BIT_MASK(1) << GPIO_PADS_OUTPUT_DISABLE_SHIFT)
 
/* Reserved bits in the RP1 pad control register. */
#define GPIO_PADS_RESERVED_MASK GENMASK(31, 8)

 
#endif /* ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_RP1_H */