Zephyr Project API 4.4.99
A Scalable Open Source RTOS
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Files

file  memory-attr-arm64.h
 ARM64 specific memory attribute definitions for devicetree.

Macros

#define DT_MEM_ARM64_GET(x)
 Extract ARM64-specific bits from a full zephyr,memory-attr value.
#define DT_MEM_ARM64_MMU_NORMAL_NC   (0)
 Normal non-cacheable memory.
#define DT_MEM_ARM64_MMU_NORMAL_WT   (DT_MEM_CACHEABLE)
 Normal write-through cacheable memory.
#define DT_MEM_ARM64_MMU_NORMAL
 Normal write-back cacheable memory.
#define DT_MEM_ARM64_MMU_UNKNOWN   DT_MEM_ARCH_ATTR_UNKNOWN
 DT value for unknown or unsupported memory type.

Detailed Description

Macro Definition Documentation

◆ DT_MEM_ARM64_GET

#define DT_MEM_ARM64_GET ( x)

#include <memory-attr-arm64.h>

Value:
((x) & DT_MEM_ARM64_MASK)

Extract ARM64-specific bits from a full zephyr,memory-attr value.

Parameters
xValue to extract ARM64-specific memory attribute bits from.
Returns
ARM64-specific memory attribute bits.

◆ DT_MEM_ARM64_MMU_NORMAL

#define DT_MEM_ARM64_MMU_NORMAL

#include <memory-attr-arm64.h>

Value:
DT_MEM_ARM64(ATTR_ARM64_CACHE_WB))
#define DT_MEM_CACHEABLE
Memory is cacheable.
Definition memory-attr.h:48

Normal write-back cacheable memory.

◆ DT_MEM_ARM64_MMU_NORMAL_NC

#define DT_MEM_ARM64_MMU_NORMAL_NC   (0)

#include <memory-attr-arm64.h>

Normal non-cacheable memory.

◆ DT_MEM_ARM64_MMU_NORMAL_WT

#define DT_MEM_ARM64_MMU_NORMAL_WT   (DT_MEM_CACHEABLE)

#include <memory-attr-arm64.h>

Normal write-through cacheable memory.

◆ DT_MEM_ARM64_MMU_UNKNOWN

#define DT_MEM_ARM64_MMU_UNKNOWN   DT_MEM_ARCH_ATTR_UNKNOWN

#include <memory-attr-arm64.h>

DT value for unknown or unsupported memory type.