Zephyr Project API 4.4.99
A Scalable Open Source RTOS
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EM32 Clock Gating IDs
Device Model

Clock gating IDs for EM32 platform peripherals. More...

Macros

#define EM32_GATE_HCLKG_DMA   0x00
 DMA HCLK gating ID.
#define EM32_GATE_HCLKG_GPIOA   0x01
 GPIO Port A HCLK gating ID.
#define EM32_GATE_HCLKG_GPIOB   0x02
 GPIO Port B HCLK gating ID.
#define EM32_GATE_HCLKG_7816_1   0x04
 ISO7816-1 Interface HCLK gating ID.
#define EM32_GATE_HCLKG_7816_2   0x05
 ISO7816-2 Interface HCLK gating ID.
#define EM32_GATE_HCLKG_ENCRYPT   0x06
 Encryption Engine HCLK gating ID.
#define EM32_GATE_HCLKG_ESPI1   0x0F
 eSPI Interface HCLK gating ID
#define EM32_GATE_HCLKG_EXTSPI   0x1F
 External SPI Interface HCLK gating ID.
#define EM32_GATE_HCLKG_GHM_ACC1   0x20
 GHM Accelerator 1 HCLK gating ID.
#define EM32_GATE_HCLKG_GHM_ACC2   0x21
 GHM Accelerator 2 HCLK gating ID.
#define EM32_GATE_HCLKG_GHM_ACC3   0x22
 GHM Accelerator 3 HCLK gating ID.
#define EM32_GATE_HCLKF_GHM_IP   0x23
 GHM IP HCLKF gating ID.
#define EM32_GATE_HCLKF_FLASH_BIST   0x24
 Flash BIST HCLKF gating ID.
#define EM32_GATE_HCLKF_GHM_RANSAC   0x25
 GHM RANSAC HCLKF gating ID.
#define EM32_GATE_HCLKF_SWSPI   0x26
 Software SPI HCLKF gating ID.
#define EM32_GATE_HCLKF_GHM_DOUBLE   0x27
 GHM Double Processing HCLKF gating ID.
#define EM32_GATE_HCLKF_GHM_DISTINGUISH   0x28
 GHM Distinguish HCLKF gating ID.
#define EM32_GATE_HCLKF_GHM_LSE   0x29
 GHM Least Squares Estimation HCLKF gating ID.
#define EM32_GATE_HCLKF_GHM_SAD   0x2A
 GHM Sum of Absolute Differences HCLKF gating ID.
#define EM32_GATE_HCLKF_GHM_M2D   0x2B
 GHM Motion-to-Depth HCLKF gating ID.
#define EM32_GATE_PCLKG_LPC   0x03
 LPC Controller PCLK gating ID.
#define EM32_GATE_PCLKG_USART   0x07
 USART PCLK gating ID.
#define EM32_GATE_PCLKG_TMR1   0x08
 Timer 1 PCLK gating ID.
#define EM32_GATE_PCLKG_TMR2   0x09
 Timer 2 PCLK gating ID.
#define EM32_GATE_PCLKG_TMR3   0x0A
 Timer 3 PCLK gating ID.
#define EM32_GATE_PCLKG_TMR4   0x0B
 Timer 4 PCLK gating ID.
#define EM32_GATE_PCLKG_UART1   0x0C
 UART 1 PCLK gating ID.
#define EM32_GATE_PCLKG_UART2   0x0D
 UART 2 PCLK gating ID.
#define EM32_GATE_PCLKG_RVD1   0x0E
 RVD 1 PCLK gating ID.
#define EM32_GATE_PCLKG_SSP2   0x10
 SSP 2 PCLK gating ID.
#define EM32_GATE_PCLKG_I2C1   0x11
 I2C 1 PCLK gating ID.
#define EM32_GATE_PCLKG_I2C2   0x12
 I2C 2 PCLK gating ID.
#define EM32_GATE_PCLKG_PWM   0x13
 PWM PCLK gating ID.
#define EM32_GATE_PCLKG_RVD2   0x14
 RVD 2 PCLK gating ID.
#define EM32_GATE_PCLKG_UDC   0x15
 USB Device Controller PCLK gating ID.
#define EM32_GATE_PCLKG_ATRIM   0x16
 Analog Trim PCLK gating ID.
#define EM32_GATE_PCLKG_RTC   0x17
 RTC PCLK gating ID.
#define EM32_GATE_PCLKG_BKP   0x18
 Backup Register PCLK gating ID.
#define EM32_GATE_PCLKG_DWG   0x19
 Debug/Watch Dog PCLK gating ID.
#define EM32_GATE_PCLKG_PWR   0x1A
 Power Management PCLK gating ID.
#define EM32_GATE_PCLKG_CACHE   0x1B
 Cache Controller PCLK gating ID.
#define EM32_GATE_PCLKG_AIP   0x1C
 AES IP PCLK gating ID.
#define EM32_GATE_PCLKG_ECC   0x1D
 ECC Engine PCLK gating ID.
#define EM32_GATE_PCLKG_TRNG   0x1E
 TRNG PCLK gating ID.
#define EM32_GATE_PCLKG_SSP1   0x30
 SSP 1 PCLK gating ID.
#define EM32_GATE_NONE   0xFFFE
 No clock gating (invalid/reserved ID).
#define EM32_GATE_PCLKG_ALL   0xFFFF
 Enable all peripheral PCLK gates.

Detailed Description

Clock gating IDs for EM32 platform peripherals.

These IDs are used in DTS (Device Tree Source) to define which peripherals have clock gating enabled for power management.

Macro Definition Documentation

◆ EM32_GATE_HCLKF_FLASH_BIST

#define EM32_GATE_HCLKF_FLASH_BIST   0x24

#include <em32_clock.h>

Flash BIST HCLKF gating ID.

◆ EM32_GATE_HCLKF_GHM_DISTINGUISH

#define EM32_GATE_HCLKF_GHM_DISTINGUISH   0x28

#include <em32_clock.h>

GHM Distinguish HCLKF gating ID.

◆ EM32_GATE_HCLKF_GHM_DOUBLE

#define EM32_GATE_HCLKF_GHM_DOUBLE   0x27

#include <em32_clock.h>

GHM Double Processing HCLKF gating ID.

◆ EM32_GATE_HCLKF_GHM_IP

#define EM32_GATE_HCLKF_GHM_IP   0x23

#include <em32_clock.h>

GHM IP HCLKF gating ID.

◆ EM32_GATE_HCLKF_GHM_LSE

#define EM32_GATE_HCLKF_GHM_LSE   0x29

#include <em32_clock.h>

GHM Least Squares Estimation HCLKF gating ID.

◆ EM32_GATE_HCLKF_GHM_M2D

#define EM32_GATE_HCLKF_GHM_M2D   0x2B

#include <em32_clock.h>

GHM Motion-to-Depth HCLKF gating ID.

◆ EM32_GATE_HCLKF_GHM_RANSAC

#define EM32_GATE_HCLKF_GHM_RANSAC   0x25

#include <em32_clock.h>

GHM RANSAC HCLKF gating ID.

◆ EM32_GATE_HCLKF_GHM_SAD

#define EM32_GATE_HCLKF_GHM_SAD   0x2A

#include <em32_clock.h>

GHM Sum of Absolute Differences HCLKF gating ID.

◆ EM32_GATE_HCLKF_SWSPI

#define EM32_GATE_HCLKF_SWSPI   0x26

#include <em32_clock.h>

Software SPI HCLKF gating ID.

◆ EM32_GATE_HCLKG_7816_1

#define EM32_GATE_HCLKG_7816_1   0x04

#include <em32_clock.h>

ISO7816-1 Interface HCLK gating ID.

◆ EM32_GATE_HCLKG_7816_2

#define EM32_GATE_HCLKG_7816_2   0x05

#include <em32_clock.h>

ISO7816-2 Interface HCLK gating ID.

◆ EM32_GATE_HCLKG_DMA

#define EM32_GATE_HCLKG_DMA   0x00

#include <em32_clock.h>

DMA HCLK gating ID.

◆ EM32_GATE_HCLKG_ENCRYPT

#define EM32_GATE_HCLKG_ENCRYPT   0x06

#include <em32_clock.h>

Encryption Engine HCLK gating ID.

◆ EM32_GATE_HCLKG_ESPI1

#define EM32_GATE_HCLKG_ESPI1   0x0F

#include <em32_clock.h>

eSPI Interface HCLK gating ID

◆ EM32_GATE_HCLKG_EXTSPI

#define EM32_GATE_HCLKG_EXTSPI   0x1F

#include <em32_clock.h>

External SPI Interface HCLK gating ID.

◆ EM32_GATE_HCLKG_GHM_ACC1

#define EM32_GATE_HCLKG_GHM_ACC1   0x20

#include <em32_clock.h>

GHM Accelerator 1 HCLK gating ID.

◆ EM32_GATE_HCLKG_GHM_ACC2

#define EM32_GATE_HCLKG_GHM_ACC2   0x21

#include <em32_clock.h>

GHM Accelerator 2 HCLK gating ID.

◆ EM32_GATE_HCLKG_GHM_ACC3

#define EM32_GATE_HCLKG_GHM_ACC3   0x22

#include <em32_clock.h>

GHM Accelerator 3 HCLK gating ID.

◆ EM32_GATE_HCLKG_GPIOA

#define EM32_GATE_HCLKG_GPIOA   0x01

#include <em32_clock.h>

GPIO Port A HCLK gating ID.

◆ EM32_GATE_HCLKG_GPIOB

#define EM32_GATE_HCLKG_GPIOB   0x02

#include <em32_clock.h>

GPIO Port B HCLK gating ID.

◆ EM32_GATE_NONE

#define EM32_GATE_NONE   0xFFFE

#include <em32_clock.h>

No clock gating (invalid/reserved ID).

◆ EM32_GATE_PCLKG_AIP

#define EM32_GATE_PCLKG_AIP   0x1C

#include <em32_clock.h>

AES IP PCLK gating ID.

◆ EM32_GATE_PCLKG_ALL

#define EM32_GATE_PCLKG_ALL   0xFFFF

#include <em32_clock.h>

Enable all peripheral PCLK gates.

◆ EM32_GATE_PCLKG_ATRIM

#define EM32_GATE_PCLKG_ATRIM   0x16

#include <em32_clock.h>

Analog Trim PCLK gating ID.

◆ EM32_GATE_PCLKG_BKP

#define EM32_GATE_PCLKG_BKP   0x18

#include <em32_clock.h>

Backup Register PCLK gating ID.

◆ EM32_GATE_PCLKG_CACHE

#define EM32_GATE_PCLKG_CACHE   0x1B

#include <em32_clock.h>

Cache Controller PCLK gating ID.

◆ EM32_GATE_PCLKG_DWG

#define EM32_GATE_PCLKG_DWG   0x19

#include <em32_clock.h>

Debug/Watch Dog PCLK gating ID.

◆ EM32_GATE_PCLKG_ECC

#define EM32_GATE_PCLKG_ECC   0x1D

#include <em32_clock.h>

ECC Engine PCLK gating ID.

◆ EM32_GATE_PCLKG_I2C1

#define EM32_GATE_PCLKG_I2C1   0x11

#include <em32_clock.h>

I2C 1 PCLK gating ID.

◆ EM32_GATE_PCLKG_I2C2

#define EM32_GATE_PCLKG_I2C2   0x12

#include <em32_clock.h>

I2C 2 PCLK gating ID.

◆ EM32_GATE_PCLKG_LPC

#define EM32_GATE_PCLKG_LPC   0x03

#include <em32_clock.h>

LPC Controller PCLK gating ID.

◆ EM32_GATE_PCLKG_PWM

#define EM32_GATE_PCLKG_PWM   0x13

#include <em32_clock.h>

PWM PCLK gating ID.

◆ EM32_GATE_PCLKG_PWR

#define EM32_GATE_PCLKG_PWR   0x1A

#include <em32_clock.h>

Power Management PCLK gating ID.

◆ EM32_GATE_PCLKG_RTC

#define EM32_GATE_PCLKG_RTC   0x17

#include <em32_clock.h>

RTC PCLK gating ID.

◆ EM32_GATE_PCLKG_RVD1

#define EM32_GATE_PCLKG_RVD1   0x0E

#include <em32_clock.h>

RVD 1 PCLK gating ID.

◆ EM32_GATE_PCLKG_RVD2

#define EM32_GATE_PCLKG_RVD2   0x14

#include <em32_clock.h>

RVD 2 PCLK gating ID.

◆ EM32_GATE_PCLKG_SSP1

#define EM32_GATE_PCLKG_SSP1   0x30

#include <em32_clock.h>

SSP 1 PCLK gating ID.

◆ EM32_GATE_PCLKG_SSP2

#define EM32_GATE_PCLKG_SSP2   0x10

#include <em32_clock.h>

SSP 2 PCLK gating ID.

◆ EM32_GATE_PCLKG_TMR1

#define EM32_GATE_PCLKG_TMR1   0x08

#include <em32_clock.h>

Timer 1 PCLK gating ID.

◆ EM32_GATE_PCLKG_TMR2

#define EM32_GATE_PCLKG_TMR2   0x09

#include <em32_clock.h>

Timer 2 PCLK gating ID.

◆ EM32_GATE_PCLKG_TMR3

#define EM32_GATE_PCLKG_TMR3   0x0A

#include <em32_clock.h>

Timer 3 PCLK gating ID.

◆ EM32_GATE_PCLKG_TMR4

#define EM32_GATE_PCLKG_TMR4   0x0B

#include <em32_clock.h>

Timer 4 PCLK gating ID.

◆ EM32_GATE_PCLKG_TRNG

#define EM32_GATE_PCLKG_TRNG   0x1E

#include <em32_clock.h>

TRNG PCLK gating ID.

◆ EM32_GATE_PCLKG_UART1

#define EM32_GATE_PCLKG_UART1   0x0C

#include <em32_clock.h>

UART 1 PCLK gating ID.

◆ EM32_GATE_PCLKG_UART2

#define EM32_GATE_PCLKG_UART2   0x0D

#include <em32_clock.h>

UART 2 PCLK gating ID.

◆ EM32_GATE_PCLKG_UDC

#define EM32_GATE_PCLKG_UDC   0x15

#include <em32_clock.h>

USB Device Controller PCLK gating ID.

◆ EM32_GATE_PCLKG_USART

#define EM32_GATE_PCLKG_USART   0x07

#include <em32_clock.h>

USART PCLK gating ID.