Xtensa Memory Management Unit (MMU) APIs

Data Structures
struct	xtensa_mmu_range
	Struct used to map a memory region. More...

Macros
#define	XTENSA_MMU_MAP_USER   BIT(4)
	Software only bit to indicate a memory region can be accessed by user thread(s).
#define	XTENSA_MMU_MAP_SHARED   BIT(30)
	Software only bit to indicate a memory region is shared by all threads.

Functions
void	xtensa_mmu_init (void)
	Initialize hardware MMU.
void	xtensa_mmu_reinit (void)
	Re-initialize hardware MMU.
void	xtensa_mmu_tlb_ipi (void)
	Tell other processors to flush TLBs.
void	xtensa_mmu_tlb_shootdown (void)
	Invalidate cache to page tables and flush TLBs.

Variables
const struct xtensa_mmu_range	xtensa_soc_mmu_ranges []
	Additional memory regions required by SoC.
int	xtensa_soc_mmu_ranges_num
	Number of SoC additional memory regions.

Memory domain and partitions
typedef uint32_t	k_mem_partition_attr_t
#define	K_MEM_PARTITION_IS_EXECUTABLE(attr)   (((attr) & XTENSA_MMU_PERM_X) != 0)
#define	K_MEM_PARTITION_IS_WRITABLE(attr)   (((attr) & XTENSA_MMU_PERM_W) != 0)
#define	K_MEM_PARTITION_IS_USER(attr)   (((attr) & XTENSA_MMU_MAP_USER) != 0)
#define	K_MEM_PARTITION_P_RW_U_RW    ((k_mem_partition_attr_t) {XTENSA_MMU_PERM_W | XTENSA_MMU_MAP_USER})
#define	K_MEM_PARTITION_P_RW_U_NA    ((k_mem_partition_attr_t) {0})
#define	K_MEM_PARTITION_P_RO_U_RO    ((k_mem_partition_attr_t) {XTENSA_MMU_MAP_USER})
#define	K_MEM_PARTITION_P_RO_U_NA    ((k_mem_partition_attr_t) {0})
#define	K_MEM_PARTITION_P_NA_U_NA    ((k_mem_partition_attr_t) {0})
#define	K_MEM_PARTITION_P_RX_U_RX    ((k_mem_partition_attr_t) {XTENSA_MMU_PERM_X})

Memory region permission and caching mode.
#define	XTENSA_MMU_PERM_X   BIT(0)
	Memory region is executable.
#define	XTENSA_MMU_PERM_W   BIT(1)
	Memory region is writable.
#define	XTENSA_MMU_PERM_WX   (XTENSA_MMU_PERM_W | XTENSA_MMU_PERM_X)
	Memory region is both executable and writable.
#define	XTENSA_MMU_CACHED_WB   BIT(2)
	Memory region has write-back cache.
#define	XTENSA_MMU_CACHED_WT   BIT(3)
	Memory region has write-through cache.

Detailed Description

Macro Definition Documentation

K_MEM_PARTITION_IS_EXECUTABLE

#define K_MEM_PARTITION_IS_EXECUTABLE

(

attr

)

(((attr) & XTENSA_MMU_PERM_X) != 0)

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

K_MEM_PARTITION_IS_USER

#define K_MEM_PARTITION_IS_USER

(

attr

)

(((attr) & XTENSA_MMU_MAP_USER) != 0)

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

K_MEM_PARTITION_IS_WRITABLE

#define K_MEM_PARTITION_IS_WRITABLE

(

attr

)

(((attr) & XTENSA_MMU_PERM_W) != 0)

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

K_MEM_PARTITION_P_NA_U_NA

#define K_MEM_PARTITION_P_NA_U_NA    ((k_mem_partition_attr_t) {0})

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

K_MEM_PARTITION_P_RO_U_NA

#define K_MEM_PARTITION_P_RO_U_NA    ((k_mem_partition_attr_t) {0})

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

K_MEM_PARTITION_P_RO_U_RO

#define K_MEM_PARTITION_P_RO_U_RO    ((k_mem_partition_attr_t) {XTENSA_MMU_MAP_USER})

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

K_MEM_PARTITION_P_RW_U_NA

#define K_MEM_PARTITION_P_RW_U_NA    ((k_mem_partition_attr_t) {0})

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

K_MEM_PARTITION_P_RW_U_RW

#define K_MEM_PARTITION_P_RW_U_RW    ((k_mem_partition_attr_t) {XTENSA_MMU_PERM_W | XTENSA_MMU_MAP_USER})

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

K_MEM_PARTITION_P_RX_U_RX

#define K_MEM_PARTITION_P_RX_U_RX    ((k_mem_partition_attr_t) {XTENSA_MMU_PERM_X})

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

XTENSA_MMU_CACHED_WB

#define XTENSA_MMU_CACHED_WB   BIT(2)

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

Memory region has write-back cache.

XTENSA_MMU_CACHED_WT

#define XTENSA_MMU_CACHED_WT   BIT(3)

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

Memory region has write-through cache.

XTENSA_MMU_MAP_SHARED

#define XTENSA_MMU_MAP_SHARED   BIT(30)

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

Software only bit to indicate a memory region is shared by all threads.

This BIT tells the mapping code whether the memory region should be shared between all threads. That is not used in the HW, it is just for the implementation.

The PTE mapping this memory will use an ASID that is set in the ring 4 spot in RASID.

XTENSA_MMU_MAP_USER

#define XTENSA_MMU_MAP_USER   BIT(4)

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

Software only bit to indicate a memory region can be accessed by user thread(s).

This BIT tells the mapping code which ring PTE entries to use.

XTENSA_MMU_PERM_W

#define XTENSA_MMU_PERM_W   BIT(1)

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

Memory region is writable.

XTENSA_MMU_PERM_WX

#define XTENSA_MMU_PERM_WX   (XTENSA_MMU_PERM_W | XTENSA_MMU_PERM_X)

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

Memory region is both executable and writable.

XTENSA_MMU_PERM_X

#define XTENSA_MMU_PERM_X   BIT(0)

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

Memory region is executable.

Typedef Documentation

k_mem_partition_attr_t

typedef uint32_t k_mem_partition_attr_t

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

Function Documentation

xtensa_mmu_init()

void xtensa_mmu_init

(

void

)

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

Initialize hardware MMU.

This initializes the MMU hardware and setup the memory regions at boot.

xtensa_mmu_reinit()

void xtensa_mmu_reinit

(

void

)

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

Re-initialize hardware MMU.

This configures the MMU hardware when the cpu lost context and has re-started.

It assumes that the page table is already created and accessible in memory.

xtensa_mmu_tlb_ipi()

void xtensa_mmu_tlb_ipi

(

void

)

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

Tell other processors to flush TLBs.

This sends IPI to other processors to telling them to invalidate cache to page tables and flush TLBs. This is needed when one processor is updating page tables that may affect threads running on other processors.

Note

This needs to be implemented in the SoC layer.

xtensa_mmu_tlb_shootdown()

void xtensa_mmu_tlb_shootdown

(

void

)

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

Invalidate cache to page tables and flush TLBs.

This invalidates cache to all page tables and flush TLBs as they may have been modified by other processors.

Variable Documentation

xtensa_soc_mmu_ranges

const struct xtensa_mmu_range xtensa_soc_mmu_ranges[]

extern

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

Additional memory regions required by SoC.

These memory regions will be setup by MMU initialization code at boot.

xtensa_soc_mmu_ranges_num

int xtensa_soc_mmu_ranges_num

extern

#include <include/zephyr/arch/xtensa/xtensa_mmu.h>

Number of SoC additional memory regions.