Zephyr Project API 4.2.99
A Scalable Open Source RTOS
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ifx_clock_source_def.h
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1/*
2 * Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#define CLK_SOURCE_IHO
9#define CLK_SOURCE_PILO
10
11#define IFX_CAT1_CLOCK_BLOCK_IHO 1
12#define IFX_CAT1_CLOCK_BLOCK_IMO 2
13#define IFX_CAT1_CLOCK_BLOCK_ECO 3
14#define IFX_CAT1_CLOCK_BLOCK_EXT 4
15#define IFX_CAT1_CLOCK_BLOCK_ALTHF 5
16#define IFX_CAT1_CLOCK_BLOCK_ALTLF 6
17#define IFX_CAT1_CLOCK_BLOCK_ILO 7
18#define IFX_CAT1_CLOCK_BLOCK_PILO 8
19#define IFX_CAT1_CLOCK_BLOCK_WCO 9
20#define IFX_CAT1_CLOCK_BLOCK_MFO 10
22#define IFX_CAT1_CLOCK_BLOCK_PATHMUX 11
24#define IFX_CAT1_CLOCK_BLOCK_FLL 12
25#define IFX_CAT1_CLOCK_BLOCK_PLL200 13
26#define IFX_CAT1_CLOCK_BLOCK_PLL400 14
27#define IFX_CAT1_CLOCK_BLOCK_ECO_PRESCALER 15
29#define IFX_CAT1_CLOCK_BLOCK_LF 16
30#define IFX_CAT1_CLOCK_BLOCK_MF 17
31#define IFX_CAT1_CLOCK_BLOCK_HF 18
33#define IFX_CAT1_CLOCK_BLOCK_PUMP 19
34#define IFX_CAT1_CLOCK_BLOCK_BAK 20
35#define IFX_CAT1_CLOCK_BLOCK_ALT_SYS_TICK 21
36#define IFX_CAT1_CLOCK_BLOCK_PERI 22
38#define IFX_CAT1_CLKHF_NO_DIVIDE 0
39#define IFX_CAT1_CLKHF_DIVIDE_BY_2 1
40#define IFX_CAT1_CLKHF_DIVIDE_BY_3 2
41#define IFX_CAT1_CLKHF_DIVIDE_BY_4 3
42#define IFX_CAT1_CLKHF_DIVIDE_BY_5 4
43#define IFX_CAT1_CLKHF_DIVIDE_BY_6 5
44#define IFX_CAT1_CLKHF_DIVIDE_BY_7 6
45#define IFX_CAT1_CLKHF_DIVIDE_BY_8 7
46#define IFX_CAT1_CLKHF_DIVIDE_BY_9 8
47#define IFX_CAT1_CLKHF_DIVIDE_BY_10 9
48#define IFX_CAT1_CLKHF_DIVIDE_BY_11 10
49#define IFX_CAT1_CLKHF_DIVIDE_BY_12 11
50#define IFX_CAT1_CLKHF_DIVIDE_BY_13 12
51#define IFX_CAT1_CLKHF_DIVIDE_BY_14 13
52#define IFX_CAT1_CLKHF_DIVIDE_BY_15 14
53#define IFX_CAT1_CLKHF_DIVIDE_BY_16 15
54#define IFX_CAT1_CLKHF_MAX_DIVIDER
56#define IFX_CAT1_CLKPATH_IN_IMO 0
57#define IFX_CAT1_CLKPATH_IN_EXT 1
58#define IFX_CAT1_CLKPATH_IN_ECO 2
59#define IFX_CAT1_CLKPATH_IN_ALTHF 3
60/* Select the DSI MUX output as the output of the path mux */
61#define IFX_CAT1_CLKPATH_IN_DSIMUX 4
62#define IFX_CAT1_CLKPATH_IN_LPECO 5
63#define IFX_CAT1_CLKPATH_IN_IHO 6
64/* Select a DSI signal (0 - 15) as the output of the DSI mux and path mux. \
65 * Make sure the DSI clock sources are available on used device. \
66 */
67#define IFX_CAT1_CLKPATH_IN_DSI 0x100
69#define IFX_CAT1_CLKPATH_IN_ILO 0x110
71#define IFX_CAT1_CLKPATH_IN_WCO 0x111
75#define IFX_CAT1_CLKPATH_IN_ALTLF 0x112
79#define IFX_CAT1_CLKPATH_IN_PILO 0x113
81#define IFX_CAT1_CLKPATH_IN_ILO1 0x114