Zephyr Project API
4.2.0
A Scalable Open Source RTOS
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imx8qm-pinctrl.h
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/*
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* Copyright 2023, 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QM_PINCTRL_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QM_PINCTRL_H_
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/* values for pad field */
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#define SC_P_UART0_RTS_B 23
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#define SC_P_UART0_CTS_B 24
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#define SC_P_ESAI0_FSR 104
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#define SC_P_ESAI0_FST 105
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#define SC_P_ESAI0_SCKR 106
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#define SC_P_ESAI0_SCKT 107
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#define SC_P_ESAI0_TX0 108
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#define SC_P_ESAI0_TX1 109
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#define SC_P_ESAI0_TX2_RX3 110
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#define SC_P_ESAI0_TX3_RX2 111
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#define SC_P_ESAI0_TX4_RX1 112
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#define SC_P_ESAI0_TX5_RX0 113
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#define SC_P_SAI1_RXD 128
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#define SC_P_SAI1_TXC 130
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#define SC_P_SAI1_TXD 131
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#define SC_P_SAI1_TXFS 132
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/* mux values */
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#define IMX8QM_DMA_LPUART2_RX_UART0_RTS_B 2
/* UART0_RTS_B ---> DMA_LPUART2_RX */
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#define IMX8QM_DMA_LPUART2_TX_UART0_CTS_B 2
/* DMA_LPUART2_TX ---> UART0_CTS_B */
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#define IMX8QM_AUD_SAI1_RXD_SAI1_RXD 0
/* AUD_SAI1_RXD <--- SAI1_RXD */
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#define IMX8QM_AUD_SAI1_TXC_SAI1_TXC 0
/* AUD_SAI1_TXC <---> SAI1_TXC */
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#define IMX8QM_AUD_SAI1_TXD_SAI1_TXD 0
/* AUD_SAI1_TXD ---> SAI1_TXD */
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#define IMX8QM_AUD_SAI1_TXFS_SAI1_TXFS 0
/* AUD_SAI1_TXFS <---> SAI1_TXFS */
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#define IMX8QM_AUD_ESAI0_FSR_ESAI0_FSR 0
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#define IMX8QM_AUD_ESAI0_FST_ESAI0_FST 0
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#define IMX8QM_AUD_ESAI0_SCKR_ESAI0_SCKR 0
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#define IMX8QM_AUD_ESAI0_SCKT_ESAI0_SCKT 0
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#define IMX8QM_AUD_ESAI0_TX0_ESAI_TX0 0
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#define IMX8QM_AUD_ESAI0_TX1_ESAI_TX1 0
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#define IMX8QM_AUD_ESAI0_TX2_RX3_ESAI0_TX2_RX3 0
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#define IMX8QM_AUD_ESAI0_TX3_RX2_ESAI0_TX3_RX2 0
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#define IMX8QM_AUD_ESAI0_TX4_RX1_ESAI0_TX4_RX1 0
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#define IMX8QM_AUD_ESAI0_TX5_RX0_ESAI0_TX5_RX0 0
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QM_PINCTRL_H_ */
include
zephyr
dt-bindings
pinctrl
imx8qm-pinctrl.h
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