Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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mcux_lpc_syscon_clock.h
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1/*
2 * Copyright 2020-2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_
8#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_
9
10/* Note- clock identifiers in this file must be unique,
11 * as the driver uses them in a switch case
12 */
13
14#define MCUX_LPC_CLK_ID(high, low) ((high << 8) | (low))
15
16/* These IDs are used within SOC macros, and thus cannot be defined
17 * using the standard MCUX_LPC_CLK_ID form
18 */
19#define MCUX_CTIMER0_CLK 0
20#define MCUX_CTIMER1_CLK 1
21#define MCUX_CTIMER2_CLK 2
22#define MCUX_CTIMER3_CLK 3
23#define MCUX_CTIMER4_CLK 4
24
25#define MCUX_FLEXCOMM0_CLK MCUX_LPC_CLK_ID(0x01, 0x00)
26#define MCUX_FLEXCOMM1_CLK MCUX_LPC_CLK_ID(0x01, 0x01)
27#define MCUX_FLEXCOMM2_CLK MCUX_LPC_CLK_ID(0x01, 0x02)
28#define MCUX_FLEXCOMM3_CLK MCUX_LPC_CLK_ID(0x01, 0x03)
29#define MCUX_FLEXCOMM4_CLK MCUX_LPC_CLK_ID(0x01, 0x04)
30#define MCUX_FLEXCOMM5_CLK MCUX_LPC_CLK_ID(0x01, 0x05)
31#define MCUX_FLEXCOMM6_CLK MCUX_LPC_CLK_ID(0x01, 0x06)
32#define MCUX_FLEXCOMM7_CLK MCUX_LPC_CLK_ID(0x01, 0x07)
33#define MCUX_FLEXCOMM8_CLK MCUX_LPC_CLK_ID(0x01, 0x08)
34#define MCUX_FLEXCOMM9_CLK MCUX_LPC_CLK_ID(0x01, 0x09)
35#define MCUX_FLEXCOMM10_CLK MCUX_LPC_CLK_ID(0x01, 0x0A)
36#define MCUX_FLEXCOMM11_CLK MCUX_LPC_CLK_ID(0x01, 0x0B)
37#define MCUX_FLEXCOMM12_CLK MCUX_LPC_CLK_ID(0x01, 0x0C)
38#define MCUX_FLEXCOMM13_CLK MCUX_LPC_CLK_ID(0x01, 0x0D)
39#define MCUX_HS_SPI_CLK MCUX_LPC_CLK_ID(0x01, 0x0E)
40#define MCUX_FLEXCOMM14_CLK MCUX_HS_SPI_CLK
41#define MCUX_PMIC_I2C_CLK MCUX_LPC_CLK_ID(0x01, 0x0F)
42#define MCUX_HS_SPI1_CLK MCUX_LPC_CLK_ID(0x01, 0x10)
43
44#define MCUX_USDHC1_CLK MCUX_LPC_CLK_ID(0x02, 0x00)
45#define MCUX_USDHC2_CLK MCUX_LPC_CLK_ID(0x02, 0x01)
46
47#define MCUX_MCAN_CLK MCUX_LPC_CLK_ID(0x03, 0x00)
48
49#define MCUX_BUS_CLK MCUX_LPC_CLK_ID(0x04, 0x00)
50
51#define MCUX_SDIF_CLK MCUX_LPC_CLK_ID(0x05, 0x00)
52
53#define MCUX_I3C_CLK MCUX_LPC_CLK_ID(0x06, 0x00)
54
55#define MCUX_MIPI_DSI_DPHY_CLK MCUX_LPC_CLK_ID(0x07, 0x00)
56#define MCUX_MIPI_DSI_ESC_CLK MCUX_LPC_CLK_ID(0x07, 0x01)
57
58#define MCUX_LCDIF_PIXEL_CLK MCUX_LPC_CLK_ID(0x08, 0x00)
59
60#define MCUX_SCTIMER_CLK MCUX_LPC_CLK_ID(0x09, 0x00)
61
62#define MCUX_DMIC_CLK MCUX_LPC_CLK_ID(0x0A, 0x00)
63
64#define MCUX_FLEXSPI_CLK MCUX_LPC_CLK_ID(0x0A, 0x00)
65#define MCUX_FLEXSPI2_CLK MCUX_LPC_CLK_ID(0x0A, 0x01)
66
67#define MCUX_MRT_CLK MCUX_LPC_CLK_ID(0x0B, 0x00)
68#define MCUX_FREEMRT_CLK MCUX_LPC_CLK_ID(0x0B, 0x01)
69
70#define MCUX_PORT0_CLK MCUX_LPC_CLK_ID(0x0C, 0x00)
71#define MCUX_PORT1_CLK MCUX_LPC_CLK_ID(0x0C, 0x01)
72#define MCUX_PORT2_CLK MCUX_LPC_CLK_ID(0x0C, 0x02)
73#define MCUX_PORT3_CLK MCUX_LPC_CLK_ID(0x0C, 0x03)
74#define MCUX_PORT4_CLK MCUX_LPC_CLK_ID(0x0C, 0x04)
75#define MCUX_PORT5_CLK MCUX_LPC_CLK_ID(0x0C, 0x05)
76
77#define MCUX_ENET_QOS_CLK MCUX_LPC_CLK_ID(0x0D, 0x00)
78
79#define MCUX_ENET_CLK MCUX_LPC_CLK_ID(0x0D, 0x80)
80#define MCUX_ENET_PLL MCUX_LPC_CLK_ID(0x0D, 0x81)
81
82#define MCUX_LCDIC_CLK MCUX_LPC_CLK_ID(0x0E, 0x00)
83
84#define MCUX_LPADC1_CLK MCUX_LPC_CLK_ID(0x0F, 0x00)
85#define MCUX_LPADC2_CLK MCUX_LPC_CLK_ID(0x0F, 0x01)
86
87#define MCUX_FLEXCAN0_CLK MCUX_LPC_CLK_ID(0x10, 0x00)
88#define MCUX_FLEXCAN1_CLK MCUX_LPC_CLK_ID(0x10, 0x01)
89
90#define MCUX_FLEXIO0_CLK MCUX_LPC_CLK_ID(0x11, 0x00)
91
92#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ */