13#ifndef __ZEPHYR_INCLUDE_DRIVERS_NPCX_FLASH_API_EX_H__
14#define __ZEPHYR_INCLUDE_DRIVERS_NPCX_FLASH_API_EX_H__
115#define NPCX_EX_OP_LOCK_UMA BIT(0)
116#define NPCX_EX_OP_INT_FLASH_WP BIT(1)
Public API for FLASH drivers.
#define FLASH_EX_OP_VENDOR_BASE
Definition flash.h:688
flash_npcx_ex_ops
Enumeration for NPCX flash extended operations.
Definition npcx_flash_api_ex.h:32
@ FLASH_NPCX_EX_OP_GET_QSPI_OPER
Get specific operation for Quad-SPI nor flash.
Definition npcx_flash_api_ex.h:66
@ FLASH_NPCX_EX_OP_SET_QSPI_OPER
Configure specific operation for Quad-SPI nor flash.
Definition npcx_flash_api_ex.h:57
@ FLASH_NPCX_EX_OP_EXEC_UMA
User Mode Access (UMA) mode execution.
Definition npcx_flash_api_ex.h:46
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
__UINT8_TYPE__ uint8_t
Definition stdint.h:88
Input parameters for FLASH_NPCX_EX_OP_SET_QSPI_OPER operation.
Definition npcx_flash_api_ex.h:97
uint32_t mask
Mask of operations to configure.
Definition npcx_flash_api_ex.h:99
bool enable
True to enable, false to disable.
Definition npcx_flash_api_ex.h:98
Output parameters for FLASH_NPCX_EX_OP_GET_QSPI_OPER operation.
Definition npcx_flash_api_ex.h:107
uint32_t oper
Bitfield of currently active operations.
Definition npcx_flash_api_ex.h:108
Input parameters for FLASH_NPCX_EX_OP_EXEC_UMA operation.
Definition npcx_flash_api_ex.h:74
size_t addr_count
Number of address bytes (0–4).
Definition npcx_flash_api_ex.h:79
uint32_t addr
Address for address phase.
Definition npcx_flash_api_ex.h:78
uint8_t * tx_buf
Pointer to transmit buffer (may be NULL).
Definition npcx_flash_api_ex.h:76
size_t rx_count
Number of bytes expected to be read.
Definition npcx_flash_api_ex.h:80
uint8_t opcode
SPI opcode (command byte).
Definition npcx_flash_api_ex.h:75
size_t tx_count
Number of bytes to transmit.
Definition npcx_flash_api_ex.h:77
Output parameters for FLASH_NPCX_EX_OP_EXEC_UMA operation.
Definition npcx_flash_api_ex.h:88
uint8_t * rx_buf
Pointer to receive buffer (must be large enough).
Definition npcx_flash_api_ex.h:89