Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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nrf-pinctrl.h
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1/*
2 * Copyright (c) 2021 Nordic Semiconductor ASA
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_
8
9/*
10 * The whole nRF pin configuration information is encoded in a 32-bit bitfield
11 * organized as follows:
12 *
13 * - 31..17: Pin function.
14 * - 16: Pin inversion mode.
15 * - 15: Pin low power mode.
16 * - 14..11: Pin output drive configuration.
17 * - 10..9: Pin pull configuration.
18 * - 8..0: Pin number (combination of port and pin).
19 */
20
27#define NRF_FUN_POS 17U
29#define NRF_FUN_MSK 0x7FFFU
31#define NRF_INVERT_POS 16U
33#define NRF_INVERT_MSK 0x1U
35#define NRF_LP_POS 15U
37#define NRF_LP_MSK 0x1U
39#define NRF_DRIVE_POS 11U
41#define NRF_DRIVE_MSK 0xFU
43#define NRF_PULL_POS 9U
45#define NRF_PULL_MSK 0x3U
47#define NRF_PIN_POS 0U
49#define NRF_PIN_MSK 0x1FFU
50
59#define NRF_FUN_UART_TX 0U
61#define NRF_FUN_UART_RX 1U
63#define NRF_FUN_UART_RTS 2U
65#define NRF_FUN_UART_CTS 3U
67#define NRF_FUN_SPIM_SCK 4U
69#define NRF_FUN_SPIM_MOSI 5U
71#define NRF_FUN_SPIM_MISO 6U
73#define NRF_FUN_SPIS_SCK 7U
75#define NRF_FUN_SPIS_MOSI 8U
77#define NRF_FUN_SPIS_MISO 9U
79#define NRF_FUN_SPIS_CSN 10U
81#define NRF_FUN_TWIM_SCL 11U
83#define NRF_FUN_TWIM_SDA 12U
85#define NRF_FUN_I2S_SCK_M 13U
87#define NRF_FUN_I2S_SCK_S 14U
89#define NRF_FUN_I2S_LRCK_M 15U
91#define NRF_FUN_I2S_LRCK_S 16U
93#define NRF_FUN_I2S_SDIN 17U
95#define NRF_FUN_I2S_SDOUT 18U
97#define NRF_FUN_I2S_MCK 19U
99#define NRF_FUN_PDM_CLK 20U
101#define NRF_FUN_PDM_DIN 21U
103#define NRF_FUN_PWM_OUT0 22U
105#define NRF_FUN_PWM_OUT1 23U
107#define NRF_FUN_PWM_OUT2 24U
109#define NRF_FUN_PWM_OUT3 25U
111#define NRF_FUN_QDEC_A 26U
113#define NRF_FUN_QDEC_B 27U
115#define NRF_FUN_QDEC_LED 28U
117#define NRF_FUN_QSPI_SCK 29U
119#define NRF_FUN_QSPI_CSN 30U
121#define NRF_FUN_QSPI_IO0 31U
123#define NRF_FUN_QSPI_IO1 32U
125#define NRF_FUN_QSPI_IO2 33U
127#define NRF_FUN_QSPI_IO3 34U
129#define NRF_FUN_EXMIF_CK 35U
131#define NRF_FUN_EXMIF_DQ0 36U
133#define NRF_FUN_EXMIF_DQ1 37U
135#define NRF_FUN_EXMIF_DQ2 38U
137#define NRF_FUN_EXMIF_DQ3 39U
139#define NRF_FUN_EXMIF_DQ4 40U
141#define NRF_FUN_EXMIF_DQ5 41U
143#define NRF_FUN_EXMIF_DQ6 42U
145#define NRF_FUN_EXMIF_DQ7 43U
147#define NRF_FUN_EXMIF_CS0 44U
149#define NRF_FUN_EXMIF_CS1 45U
151#define NRF_FUN_CAN_TX 46U
153#define NRF_FUN_CAN_RX 47U
154
163#define NRF_DRIVE_S0S1 0U
165#define NRF_DRIVE_H0S1 1U
167#define NRF_DRIVE_S0H1 2U
169#define NRF_DRIVE_H0H1 3U
171#define NRF_DRIVE_D0S1 4U
173#define NRF_DRIVE_D0H1 5U
175#define NRF_DRIVE_S0D1 6U
177#define NRF_DRIVE_H0D1 7U
179#define NRF_DRIVE_E0E1 8U
180
190#define NRF_PULL_NONE 0U
192#define NRF_PULL_DOWN 1U
194#define NRF_PULL_UP 3U
195
204#define NRF_LP_DISABLE 0U
206#define NRF_LP_ENABLE 1U
207
216#define NRF_PIN_DISCONNECTED NRF_PIN_MSK
217
227#define NRF_PSEL(fun, port, pin) \
228 ((((((port) * 32U) + (pin)) & NRF_PIN_MSK) << NRF_PIN_POS) | \
229 ((NRF_FUN_ ## fun & NRF_FUN_MSK) << NRF_FUN_POS))
230
239#define NRF_PSEL_DISCONNECTED(fun) \
240 (NRF_PIN_DISCONNECTED | \
241 ((NRF_FUN_ ## fun & NRF_FUN_MSK) << NRF_FUN_POS))
242
243#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NRF_PINCTRL_H_ */