Zephyr Project API
4.4.99
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nxp-freqme.h
Go to the documentation of this file.
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/*
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* SPDX-FileCopyrightText: 2026 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MONITOR_NXP_FREQME_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MONITOR_NXP_FREQME_H_
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#define NXP_FREQME_PMUX_SHIFT 20
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#define NXP_FREQME_SOURCE_UNCHANGED 0U
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/*
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* MCX families with separate FREQMEAS_REF (0x180) / FREQMEAS_TAR (0x184) mux
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* registers. MCXA, MCXC, MCXN, MCXL and MCXW all share this register layout;
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* only the per-source selector numbers differ, so each family has its own
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* cookie set below.
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*/
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#define NXP_FREQME_REF_REG 0x180
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#define NXP_FREQME_TAR_REG 0x184
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#define NXP_FREQME_REF(sel) ((sel) + (NXP_FREQME_REF_REG << NXP_FREQME_PMUX_SHIFT))
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#define NXP_FREQME_TAR(sel) ((sel) + (NXP_FREQME_TAR_REG << NXP_FREQME_PMUX_SHIFT))
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/*
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* MCXA selectors.
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* Devices: MCXA153, MCXA156, MCXA174, MCXA266, MCXA344, MCXA346, MCXA577 and
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* MCXC162 (identical selector numbering).
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*/
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#define NXP_FREQME_REF_CLK_IN NXP_FREQME_REF(1)
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#define NXP_FREQME_REF_FRO_12M NXP_FREQME_REF(2)
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#define NXP_FREQME_REF_FRO_HF_DIV NXP_FREQME_REF(3)
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#define NXP_FREQME_REF_CLK_16K1 NXP_FREQME_REF(5)
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#define NXP_FREQME_REF_SLOW_CLK NXP_FREQME_REF(6)
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#define NXP_FREQME_REF_CLK_IN0 NXP_FREQME_REF(7)
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#define NXP_FREQME_REF_CLK_IN1 NXP_FREQME_REF(8)
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#define NXP_FREQME_TAR_CLK_IN NXP_FREQME_TAR(1)
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#define NXP_FREQME_TAR_FRO_12M NXP_FREQME_TAR(2)
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#define NXP_FREQME_TAR_FRO_HF_DIV NXP_FREQME_TAR(3)
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#define NXP_FREQME_TAR_CLK_16K1 NXP_FREQME_TAR(5)
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#define NXP_FREQME_TAR_SLOW_CLK NXP_FREQME_TAR(6)
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#define NXP_FREQME_TAR_CLK_IN0 NXP_FREQME_TAR(7)
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#define NXP_FREQME_TAR_CLK_IN1 NXP_FREQME_TAR(8)
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/*
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* MCXN selectors.
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* Devices: MCXN236, MCXN947.
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*/
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#define NXP_FREQME_MCXN_REF_CLK_IN NXP_FREQME_REF(0)
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#define NXP_FREQME_MCXN_REF_FRO_12M NXP_FREQME_REF(1)
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#define NXP_FREQME_MCXN_REF_FRO_HF NXP_FREQME_REF(2)
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#define NXP_FREQME_MCXN_REF_OSC32K NXP_FREQME_REF(4)
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#define NXP_FREQME_MCXN_REF_CPU_AHB_CLK NXP_FREQME_REF(5)
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#define NXP_FREQME_MCXN_REF_CLK_IN0 NXP_FREQME_REF(6)
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#define NXP_FREQME_MCXN_REF_CLK_IN1 NXP_FREQME_REF(7)
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#define NXP_FREQME_MCXN_TAR_CLK_IN NXP_FREQME_TAR(0)
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#define NXP_FREQME_MCXN_TAR_FRO_12M NXP_FREQME_TAR(1)
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#define NXP_FREQME_MCXN_TAR_FRO_HF NXP_FREQME_TAR(2)
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#define NXP_FREQME_MCXN_TAR_OSC32K NXP_FREQME_TAR(4)
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#define NXP_FREQME_MCXN_TAR_CPU_AHB_CLK NXP_FREQME_TAR(5)
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#define NXP_FREQME_MCXN_TAR_CLK_IN0 NXP_FREQME_TAR(6)
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#define NXP_FREQME_MCXN_TAR_CLK_IN1 NXP_FREQME_TAR(7)
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/*
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* MCXL selectors.
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* Devices: MCXL255.
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*/
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#define NXP_FREQME_MCXL_REF_FRO_12M NXP_FREQME_REF(2)
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#define NXP_FREQME_MCXL_REF_FRO_HF_DIV NXP_FREQME_REF(3)
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#define NXP_FREQME_MCXL_REF_XTAL32K NXP_FREQME_REF(4)
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#define NXP_FREQME_MCXL_REF_CLK_16K0 NXP_FREQME_REF(5)
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#define NXP_FREQME_MCXL_REF_SLOW_CLK NXP_FREQME_REF(6)
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#define NXP_FREQME_MCXL_REF_CLK_IN0 NXP_FREQME_REF(7)
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#define NXP_FREQME_MCXL_REF_CLK_IN1 NXP_FREQME_REF(8)
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#define NXP_FREQME_MCXL_TAR_FRO_12M NXP_FREQME_TAR(2)
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#define NXP_FREQME_MCXL_TAR_FRO_HF_DIV NXP_FREQME_TAR(3)
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#define NXP_FREQME_MCXL_TAR_XTAL32K NXP_FREQME_TAR(4)
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#define NXP_FREQME_MCXL_TAR_CLK_16K0 NXP_FREQME_TAR(5)
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#define NXP_FREQME_MCXL_TAR_SLOW_CLK NXP_FREQME_TAR(6)
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#define NXP_FREQME_MCXL_TAR_CLK_IN0 NXP_FREQME_TAR(7)
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#define NXP_FREQME_MCXL_TAR_CLK_IN1 NXP_FREQME_TAR(8)
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/*
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* MCXW selectors.
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* Devices: MCXW236. A completely distinct selector set.
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*/
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#define NXP_FREQME_MCXW_REF_EXTERN_OSC NXP_FREQME_REF(0)
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#define NXP_FREQME_MCXW_REF_FRO_12M NXP_FREQME_REF(1)
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#define NXP_FREQME_MCXW_REF_FRO_32M NXP_FREQME_REF(2)
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#define NXP_FREQME_MCXW_REF_FRO_1M NXP_FREQME_REF(3)
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#define NXP_FREQME_MCXW_REF_OSC32K NXP_FREQME_REF(4)
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#define NXP_FREQME_MCXW_REF_MAIN_CLK NXP_FREQME_REF(5)
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#define NXP_FREQME_MCXW_REF_SPIFI_CLK NXP_FREQME_REF(6)
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#define NXP_FREQME_MCXW_REF_PORT0_PIN3 NXP_FREQME_REF(7)
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#define NXP_FREQME_MCXW_REF_PORT0_PIN11 NXP_FREQME_REF(8)
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#define NXP_FREQME_MCXW_REF_PORT0_PIN12 NXP_FREQME_REF(9)
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#define NXP_FREQME_MCXW_REF_PORT0_PIN14 NXP_FREQME_REF(10)
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#define NXP_FREQME_MCXW_TAR_EXTERN_OSC NXP_FREQME_TAR(0)
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#define NXP_FREQME_MCXW_TAR_FRO_12M NXP_FREQME_TAR(1)
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#define NXP_FREQME_MCXW_TAR_FRO_32M NXP_FREQME_TAR(2)
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#define NXP_FREQME_MCXW_TAR_FRO_1M NXP_FREQME_TAR(3)
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#define NXP_FREQME_MCXW_TAR_OSC32K NXP_FREQME_TAR(4)
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#define NXP_FREQME_MCXW_TAR_MAIN_CLK NXP_FREQME_TAR(5)
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#define NXP_FREQME_MCXW_TAR_SPIFI_CLK NXP_FREQME_TAR(6)
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#define NXP_FREQME_MCXW_TAR_PORT0_PIN3 NXP_FREQME_TAR(7)
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#define NXP_FREQME_MCXW_TAR_PORT0_PIN11 NXP_FREQME_TAR(8)
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#define NXP_FREQME_MCXW_TAR_PORT0_PIN12 NXP_FREQME_TAR(9)
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#define NXP_FREQME_MCXW_TAR_PORT0_PIN14 NXP_FREQME_TAR(10)
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/*
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* i.MX RT700 selectors.
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* Devices: MIMXRT798S (and RT7xx family).
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*
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* RT700 places the FREQMEAS reference / target mux registers at 0x700 / 0x704
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* (not 0x180 / 0x184 like the MCX families), so it needs its own register
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* constants and helpers.
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*/
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#define NXP_FREQME_RT7XX_REF_REG 0x700
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#define NXP_FREQME_RT7XX_TAR_REG 0x704
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#define NXP_FREQME_RT7XX_REF(sel) ((sel) + (NXP_FREQME_RT7XX_REF_REG << NXP_FREQME_PMUX_SHIFT))
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#define NXP_FREQME_RT7XX_TAR(sel) ((sel) + (NXP_FREQME_RT7XX_TAR_REG << NXP_FREQME_PMUX_SHIFT))
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#define NXP_FREQME_RT7XX_REF_OSC_CLK NXP_FREQME_RT7XX_REF(0)
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#define NXP_FREQME_RT7XX_REF_FRO1_DIV8 NXP_FREQME_RT7XX_REF(1)
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#define NXP_FREQME_RT7XX_REF_FRO1 NXP_FREQME_RT7XX_REF(2)
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#define NXP_FREQME_RT7XX_REF_LPOSC NXP_FREQME_RT7XX_REF(3)
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#define NXP_FREQME_RT7XX_REF_OSC32K NXP_FREQME_RT7XX_REF(4)
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#define NXP_FREQME_RT7XX_REF_FRO0 NXP_FREQME_RT7XX_REF(6)
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#define NXP_FREQME_RT7XX_REF_FRO2 NXP_FREQME_RT7XX_REF(7)
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#define NXP_FREQME_RT7XX_REF_GPIO_A_CLK NXP_FREQME_RT7XX_REF(8)
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#define NXP_FREQME_RT7XX_REF_GPIO_B_CLK NXP_FREQME_RT7XX_REF(9)
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#define NXP_FREQME_RT7XX_TAR_OSC_CLK NXP_FREQME_RT7XX_TAR(0)
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#define NXP_FREQME_RT7XX_TAR_FRO1_DIV8 NXP_FREQME_RT7XX_TAR(1)
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#define NXP_FREQME_RT7XX_TAR_FRO1 NXP_FREQME_RT7XX_TAR(2)
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#define NXP_FREQME_RT7XX_TAR_LPOSC NXP_FREQME_RT7XX_TAR(3)
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#define NXP_FREQME_RT7XX_TAR_OSC32K NXP_FREQME_RT7XX_TAR(4)
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#define NXP_FREQME_RT7XX_TAR_FRO0 NXP_FREQME_RT7XX_TAR(6)
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#define NXP_FREQME_RT7XX_TAR_FRO2 NXP_FREQME_RT7XX_TAR(7)
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#define NXP_FREQME_RT7XX_TAR_GPIO_A_CLK NXP_FREQME_RT7XX_TAR(8)
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#define NXP_FREQME_RT7XX_TAR_GPIO_B_CLK NXP_FREQME_RT7XX_TAR(9)
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MONITOR_NXP_FREQME_H_ */
include
zephyr
dt-bindings
clock-monitor
nxp-freqme.h
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