nxp_mcxw7x_clock.h

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/*
 * Copyright 2026 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_MCXW7X_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_MCXW7X_H_


#define MCXW_CLK_OSC32K_DISABLE 0 
#define MCXW_CLK_OSC32K_ENABLE  1 
#define MCXW_CLK_OSC32K_BYPASS  3 

#define MCXW_CLK_OSC32K_CAP_0PF  0  
#define MCXW_CLK_OSC32K_CAP_2PF  1  
#define MCXW_CLK_OSC32K_CAP_4PF  2  
#define MCXW_CLK_OSC32K_CAP_6PF  3  
#define MCXW_CLK_OSC32K_CAP_8PF  4  
#define MCXW_CLK_OSC32K_CAP_10PF 5  
#define MCXW_CLK_OSC32K_CAP_12PF 6  
#define MCXW_CLK_OSC32K_CAP_14PF 7  
#define MCXW_CLK_OSC32K_CAP_16PF 8  
#define MCXW_CLK_OSC32K_CAP_18PF 9  
#define MCXW_CLK_OSC32K_CAP_20PF 10 
#define MCXW_CLK_OSC32K_CAP_22PF 11 
#define MCXW_CLK_OSC32K_CAP_24PF 12 
#define MCXW_CLK_OSC32K_CAP_26PF 13 
#define MCXW_CLK_OSC32K_CAP_28PF 14 
#define MCXW_CLK_OSC32K_CAP_30PF 15 

#define MCXW_CLK_OSC32K_COARSE_RANGE0 0 
#define MCXW_CLK_OSC32K_COARSE_RANGE1 1 
#define MCXW_CLK_OSC32K_COARSE_RANGE2 2 
#define MCXW_CLK_OSC32K_COARSE_RANGE3 3 

#define MCXW_CLK_FIRC_DISABLE      0 
#define MCXW_CLK_FIRC_ENABLE       1 
#define MCXW_CLK_FIRC_ENABLE_IN_LP 2 

#define MCXW_CLK_FIRC_RANGE_48MHZ  0 
#define MCXW_CLK_FIRC_RANGE_64MHZ  1 
#define MCXW_CLK_FIRC_RANGE_96MHZ  2 
#define MCXW_CLK_FIRC_RANGE_192MHZ 3 

#define MCXW_CLK_SYSTEM_CLK_SRC_SOSC 1 
#define MCXW_CLK_SYSTEM_CLK_SRC_SIRC 2 
#define MCXW_CLK_SYSTEM_CLK_SRC_FIRC 3 
#define MCXW_CLK_SYSTEM_CLK_SRC_ROSC 4 

#define MCXW_CLK_DIV_NONE  0  
#define MCXW_CLK_DIV_BY_1  0  
#define MCXW_CLK_DIV_BY_2  1  
#define MCXW_CLK_DIV_BY_3  2  
#define MCXW_CLK_DIV_BY_4  3  
#define MCXW_CLK_DIV_BY_5  4  
#define MCXW_CLK_DIV_BY_6  5  
#define MCXW_CLK_DIV_BY_7  6  
#define MCXW_CLK_DIV_BY_8  7  
#define MCXW_CLK_DIV_BY_10 9  
#define MCXW_CLK_DIV_BY_11 10 
#define MCXW_CLK_DIV_BY_12 11 
#define MCXW_CLK_DIV_BY_13 12 
#define MCXW_CLK_DIV_BY_14 13 
#define MCXW_CLK_DIV_BY_15 14 
#define MCXW_CLK_DIV_BY_16 15 

#define MCXW_CLK_IP_MUX_SLOW_CLK 1 
#define MCXW_CLK_IP_MUX_FRO_6M   2 
#define MCXW_CLK_IP_MUX_FRO_192M_DIV                                                               \
        3 
#define MCXW_CLK_IP_MUX_SOSC         4 
#define MCXW_CLK_IP_MUX_32K          5 
#define MCXW_CLK_IP_MUX_FRO_200M_DIV 6 
#define MCXW_CLK_IP_MUX_1M           7 
#define MCXW_CLK_IP_MUX_NONE         0xFF 

#define MCXW_CLK_CTRL_DISABLED 0  
#define MCXW_CLK_CTRL_ENABLED  1U 

#define MCXW_CLK_LP_STALL_ALLOWED 0U 
#define MCXW_CLK_LP_NO_STALL      2U 

#define MCXW_CLK_MODE_DISABLED (MCXW_CLK_CTRL_DISABLED) 
#define MCXW_CLK_MODE_ENABLED_LP_STALL                                                             \
        (MCXW_CLK_CTRL_ENABLED | MCXW_CLK_LP_STALL_ALLOWED) 
#define MCXW_CLK_MODE_ENABLED_LP_NO_STALL                                                          \
        (MCXW_CLK_CTRL_ENABLED | MCXW_CLK_LP_NO_STALL) 


#define MCXW_CLOCK(mrcc_offset, clk_mux, clk_div, flag)                                            \
        ((((mrcc_offset) & 0xFFFF) << 16) | (((clk_mux) & 0xFF) << 8) | (((clk_div) & 0xF) << 4) | \
         (((flag) & 0xF)))
 
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_MCXW7X_H_ */