Zephyr Project API 4.1.99
A Scalable Open Source RTOS
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phy.h
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1
7/*
8 * Copyright (c) 2021 IP-Logix Inc.
9 * Copyright 2022 NXP
10 * Copyright (c) 2025 Aerlync Labs Inc.
11 *
12 * SPDX-License-Identifier: Apache-2.0
13 */
14#ifndef ZEPHYR_INCLUDE_DRIVERS_PHY_H_
15#define ZEPHYR_INCLUDE_DRIVERS_PHY_H_
16
25#include <zephyr/types.h>
26#include <zephyr/device.h>
28#include <errno.h>
29
30#ifdef __cplusplus
31extern "C" {
32#endif
33
53
61#define PHY_LINK_IS_FULL_DUPLEX(x) \
62 (x & (LINK_FULL_10BASE | LINK_FULL_100BASE | LINK_FULL_1000BASE | LINK_FULL_2500BASE | \
63 LINK_FULL_5000BASE))
64
72#define PHY_LINK_IS_SPEED_1000M(x) (x & (LINK_HALF_1000BASE | LINK_FULL_1000BASE))
73
81#define PHY_LINK_IS_SPEED_100M(x) (x & (LINK_HALF_100BASE | LINK_FULL_100BASE))
82
90#define PHY_LINK_IS_SPEED_10M(x) (x & (LINK_HALF_10BASE | LINK_FULL_10BASE))
91
99
105
123
135int genphy_get_plca_cfg(const struct device *dev, struct phy_plca_cfg *plca_cfg);
136
148int genphy_set_plca_cfg(const struct device *dev, struct phy_plca_cfg *plca_cfg);
149
161int genphy_get_plca_sts(const struct device *dev, bool *plca_status);
162
172typedef void (*phy_callback_t)(const struct device *dev, struct phy_link_state *state,
173 void *user_data);
174
181__subsystem struct ethphy_driver_api {
183 int (*get_link)(const struct device *dev, struct phy_link_state *state);
184
186 int (*cfg_link)(const struct device *dev, enum phy_link_speed adv_speeds,
188
192 int (*link_cb_set)(const struct device *dev, phy_callback_t cb, void *user_data);
193
195 int (*read)(const struct device *dev, uint16_t reg_addr, uint32_t *data);
196
198 int (*write)(const struct device *dev, uint16_t reg_addr, uint32_t data);
199
201 int (*read_c45)(const struct device *dev, uint8_t devad, uint16_t regad, uint16_t *data);
202
204 int (*write_c45)(const struct device *dev, uint8_t devad, uint16_t regad, uint16_t data);
205
206 /* Set PLCA settings */
207 int (*set_plca_cfg)(const struct device *dev, struct phy_plca_cfg *plca_cfg);
208
209 /* Get PLCA settings */
210 int (*get_plca_cfg)(const struct device *dev, struct phy_plca_cfg *plca_cfg);
211
212 /* Get PLCA status */
213 int (*get_plca_sts)(const struct device *dev, bool *plca_sts);
214};
233static inline int phy_configure_link(const struct device *dev, enum phy_link_speed speeds,
235{
236 if (DEVICE_API_GET(ethphy, dev)->cfg_link == NULL) {
237 return -ENOSYS;
238 }
239
240 /* Check if only one speed is set, when auto-negotiation is disabled */
242 return -EINVAL;
243 }
244
245 return DEVICE_API_GET(ethphy, dev)->cfg_link(dev, speeds, flags);
246}
247
261static inline int phy_get_link_state(const struct device *dev, struct phy_link_state *state)
262{
263 if (DEVICE_API_GET(ethphy, dev)->get_link == NULL) {
264 return -ENOSYS;
265 }
266
267 return DEVICE_API_GET(ethphy, dev)->get_link(dev, state);
268}
269
288static inline int phy_link_callback_set(const struct device *dev, phy_callback_t callback,
289 void *user_data)
290{
291 if (DEVICE_API_GET(ethphy, dev)->link_cb_set == NULL) {
292 return -ENOSYS;
293 }
294
295 return DEVICE_API_GET(ethphy, dev)->link_cb_set(dev, callback, user_data);
296}
297
310static inline int phy_read(const struct device *dev, uint16_t reg_addr, uint32_t *value)
311{
312 if (DEVICE_API_GET(ethphy, dev)->read == NULL) {
313 return -ENOSYS;
314 }
315
316 return DEVICE_API_GET(ethphy, dev)->read(dev, reg_addr, value);
317}
318
331static inline int phy_write(const struct device *dev, uint16_t reg_addr, uint32_t value)
332{
333 if (DEVICE_API_GET(ethphy, dev)->write == NULL) {
334 return -ENOSYS;
335 }
336
337 return DEVICE_API_GET(ethphy, dev)->write(dev, reg_addr, value);
338}
339
353static inline int phy_read_c45(const struct device *dev, uint8_t devad, uint16_t regad,
354 uint16_t *data)
355{
356 if (DEVICE_API_GET(ethphy, dev)->read_c45 == NULL) {
357 return -ENOSYS;
358 }
359
360 return DEVICE_API_GET(ethphy, dev)->read_c45(dev, devad, regad, data);
361}
362
376static inline int phy_write_c45(const struct device *dev, uint8_t devad, uint16_t regad,
378{
379 if (DEVICE_API_GET(ethphy, dev)->write_c45 == NULL) {
380 return -ENOSYS;
381 }
382
383 return DEVICE_API_GET(ethphy, dev)->write_c45(dev, devad, regad, data);
384}
385
397static inline int phy_set_plca_cfg(const struct device *dev, struct phy_plca_cfg *plca_cfg)
398{
399 if (DEVICE_API_GET(ethphy, dev)->set_plca_cfg == NULL) {
400 return -ENOSYS;
401 }
402
403 return DEVICE_API_GET(ethphy, dev)->set_plca_cfg(dev, plca_cfg);
404}
405
417static inline int phy_get_plca_cfg(const struct device *dev, struct phy_plca_cfg *plca_cfg)
418{
419 if (DEVICE_API_GET(ethphy, dev)->get_plca_cfg == NULL) {
420 return -ENOSYS;
421 }
422
423 return DEVICE_API_GET(ethphy, dev)->get_plca_cfg(dev, plca_cfg);
424}
425
437static inline int phy_get_plca_sts(const struct device *dev, bool *plca_status)
438{
439 if (DEVICE_API_GET(ethphy, dev)->get_plca_sts == NULL) {
440 return -ENOSYS;
441 }
442
443 return DEVICE_API_GET(ethphy, dev)->get_plca_sts(dev, plca_status);
444}
445
446#ifdef __cplusplus
447}
448#endif
449
454#endif /* ZEPHYR_INCLUDE_DRIVERS_PHY_H_ */
#define DEVICE_API_GET(_class, _dev)
Expands to the pointer of a device's API for a given class.
Definition device.h:1350
System error numbers.
static int phy_link_callback_set(const struct device *dev, phy_callback_t callback, void *user_data)
Set link state change callback.
Definition phy.h:288
int genphy_get_plca_cfg(const struct device *dev, struct phy_plca_cfg *plca_cfg)
Write PHY PLCA configuration.
static int phy_set_plca_cfg(const struct device *dev, struct phy_plca_cfg *plca_cfg)
Write PHY PLCA configuration.
Definition phy.h:397
static int phy_read(const struct device *dev, uint16_t reg_addr, uint32_t *value)
Read PHY registers.
Definition phy.h:310
static int phy_write_c45(const struct device *dev, uint8_t devad, uint16_t regad, uint16_t data)
Write PHY C45 register.
Definition phy.h:376
static int phy_get_link_state(const struct device *dev, struct phy_link_state *state)
Get PHY link state.
Definition phy.h:261
static int phy_read_c45(const struct device *dev, uint8_t devad, uint16_t regad, uint16_t *data)
Read PHY C45 register.
Definition phy.h:353
static int phy_write(const struct device *dev, uint16_t reg_addr, uint32_t value)
Write PHY register.
Definition phy.h:331
phy_cfg_link_flag
Ethernet configure link flags.
Definition phy.h:101
static int phy_get_plca_sts(const struct device *dev, bool *plca_status)
Read PHY PLCA status.
Definition phy.h:437
int genphy_set_plca_cfg(const struct device *dev, struct phy_plca_cfg *plca_cfg)
Read PHY PLCA configuration.
static int phy_get_plca_cfg(const struct device *dev, struct phy_plca_cfg *plca_cfg)
Read PHY PLCA configuration.
Definition phy.h:417
phy_link_speed
Ethernet link speeds.
Definition phy.h:35
void(* phy_callback_t)(const struct device *dev, struct phy_link_state *state, void *user_data)
Define the callback function signature for phy_link_callback_set() function.
Definition phy.h:172
int genphy_get_plca_sts(const struct device *dev, bool *plca_status)
Read PHY PLCA status.
static int phy_configure_link(const struct device *dev, enum phy_link_speed speeds, enum phy_cfg_link_flag flags)
Configure PHY link.
Definition phy.h:233
@ PHY_FLAG_AUTO_NEGOTIATION_DISABLED
Auto-negotiation disable.
Definition phy.h:103
@ LINK_HALF_10BASE
10Base Half-Duplex
Definition phy.h:37
@ LINK_FULL_2500BASE
2.5GBase Full-Duplex
Definition phy.h:49
@ LINK_FULL_10BASE
10Base Full-Duplex
Definition phy.h:39
@ LINK_HALF_100BASE
100Base Half-Duplex
Definition phy.h:41
@ LINK_FULL_1000BASE
1000Base Full-Duplex
Definition phy.h:47
@ LINK_HALF_1000BASE
1000Base Half-Duplex
Definition phy.h:45
@ LINK_FULL_5000BASE
5GBase Full-Duplex
Definition phy.h:51
@ LINK_FULL_100BASE
100Base Full-Duplex
Definition phy.h:43
#define BIT(n)
Unsigned integer with bit position n set (signed in assembly language).
Definition util_macro.h:44
#define IS_POWER_OF_TWO(x)
Check if a x is a power of two.
Definition util_macro.h:77
#define EINVAL
Invalid argument.
Definition errno.h:60
#define ENOSYS
Function not implemented.
Definition errno.h:82
#define NULL
Definition iar_missing_defs.h:20
flags
Definition parser.h:97
state
Definition parser_state.h:29
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
__UINT8_TYPE__ uint8_t
Definition stdint.h:88
__UINT16_TYPE__ uint16_t
Definition stdint.h:89
Runtime device structure (in ROM) per driver instance.
Definition device.h:510
void * data
Address of the device instance private data.
Definition device.h:520
PLCA (Physical Layer Collision Avoidance) Reconciliation Sublayer configurations.
Definition phy.h:107
uint8_t to_timer
PLCA to_timer in bit-times, which determines the PLCA transmit opportunity.
Definition phy.h:121
uint8_t node_count
PLCA node count.
Definition phy.h:115
uint8_t version
PLCA register map version.
Definition phy.h:109
bool enable
PLCA configured mode (enable/disable)
Definition phy.h:111
uint8_t node_id
PLCA local node identifier.
Definition phy.h:113
uint8_t burst_count
Additional frames a node is allowed to send in single transmit opportunity (TO)
Definition phy.h:117
uint8_t burst_timer
Wait time for the MAC to send a new frame before interrupting the burst.
Definition phy.h:119
Macro utilities.