Zephyr Project API 4.4.99
A Scalable Open Source RTOS
Loading...
Searching...
No Matches
pinctrl-rcar-common.h
Go to the documentation of this file.
1/*
2 * Copyright (c) 2021-2023 IoT.bzh
3 * Copyright (c) 2025 Renesas Electronics Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
13
14#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RCAR_COMMON_H_
15#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RCAR_COMMON_H_
16
21
56
72#define IPSR(bank, shift, func) (((bank) << 10U) | ((shift) << 4U) | (func))
73
75/* Arbitrary number to encode non capable gpio pin */
76#define PIN_NOGPSR_START 1024U
78
85#define RCAR_GP_PIN(bank, pin) (((bank) * 32U) + (pin))
86
92#define RCAR_NOGP_PIN(pin) (PIN_NOGPSR_START + pin)
93
105#define IPnSR(bank, reg, shift, func) \
106 IPSR(((reg) << 5U) | (bank), shift, func)
107
109#define IP0SR0(shift, func) IPnSR(0, 0, shift, func)
110#define IP1SR0(shift, func) IPnSR(1, 0, shift, func)
111#define IP2SR0(shift, func) IPnSR(2, 0, shift, func)
112#define IP3SR0(shift, func) IPnSR(3, 0, shift, func)
113#define IP0SR1(shift, func) IPnSR(0, 1, shift, func)
114#define IP1SR1(shift, func) IPnSR(1, 1, shift, func)
115#define IP2SR1(shift, func) IPnSR(2, 1, shift, func)
116#define IP3SR1(shift, func) IPnSR(3, 1, shift, func)
117#define IP0SR2(shift, func) IPnSR(0, 2, shift, func)
118#define IP1SR2(shift, func) IPnSR(1, 2, shift, func)
119#define IP2SR2(shift, func) IPnSR(2, 2, shift, func)
120#define IP3SR2(shift, func) IPnSR(3, 2, shift, func)
121#define IP0SR3(shift, func) IPnSR(0, 3, shift, func)
122#define IP1SR3(shift, func) IPnSR(1, 3, shift, func)
123#define IP2SR3(shift, func) IPnSR(2, 3, shift, func)
124#define IP3SR3(shift, func) IPnSR(3, 3, shift, func)
125#define IP0SR4(shift, func) IPnSR(0, 4, shift, func)
126#define IP1SR4(shift, func) IPnSR(1, 4, shift, func)
127#define IP2SR4(shift, func) IPnSR(2, 4, shift, func)
128#define IP3SR4(shift, func) IPnSR(3, 4, shift, func)
129#define IP0SR5(shift, func) IPnSR(0, 5, shift, func)
130#define IP1SR5(shift, func) IPnSR(1, 5, shift, func)
131#define IP2SR5(shift, func) IPnSR(2, 5, shift, func)
132#define IP3SR5(shift, func) IPnSR(3, 5, shift, func)
133#define IP0SR6(shift, func) IPnSR(0, 6, shift, func)
134#define IP1SR6(shift, func) IPnSR(1, 6, shift, func)
135#define IP2SR6(shift, func) IPnSR(2, 6, shift, func)
136#define IP3SR6(shift, func) IPnSR(3, 6, shift, func)
137#define IP0SR7(shift, func) IPnSR(0, 7, shift, func)
138#define IP1SR7(shift, func) IPnSR(1, 7, shift, func)
139#define IP2SR7(shift, func) IPnSR(2, 7, shift, func)
140#define IP3SR7(shift, func) IPnSR(3, 7, shift, func)
141#define IP0SR8(shift, func) IPnSR(0, 8, shift, func)
142#define IP1SR8(shift, func) IPnSR(1, 8, shift, func)
143#define IP2SR8(shift, func) IPnSR(2, 8, shift, func)
144#define IP3SR8(shift, func) IPnSR(3, 8, shift, func)
146
157#define IPSR_DUMMY IPnSR(0x1f, 7, 0x1f, 0xf)
158
173#define RCAR_ALTSEL_FUNC(group, pin, func) (((pin) << 14U) | ((group) << 10U) | (func))
174
179#define PIN_VOLTAGE_NONE 0
180#define PIN_VOLTAGE_1P8V 1
181#define PIN_VOLTAGE_3P3V 2
183
185
186#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RCAR_COMMON_H_ */