pinctrl-rza3m.h

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/*
 * Copyright (c) 2025 Renesas Electronics Corporation
 * SPDX-License-Identifier: Apache-2.0
 */

 
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZA3M_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZA3M_H_



 
#define PORT_00 0x0F00 
#define PORT_01 0x1000 
#define PORT_02 0x1100 
#define PORT_03 0x1200 
#define PORT_04 0x1300 
#define PORT_05 0x1400 
#define PORT_06 0x1500 
#define PORT_07 0x1600 
#define PORT_08 0x1700 
#define PORT_09 0x1800 
#define PORT_10 0x1900 
#define PORT_11 0x1A00 
#define PORT_12 0x1B00 
#define PORT_20 0x0000 
#define PORT_21 0x0100 
#define PORT_22 0x0300 
#define PORT_23 0x0400 


#define RZA_PINMUX(port, pin, func) (port | pin | (((func) - 1) << 4))

 
#define BSP_IO_NMI            0xFFFF0001 
#define BSP_IO_TMS_SWDIO      0xFFFF0200 
#define BSP_IO_SD0_CLK        0xFFFF0400 
#define BSP_IO_QSPI0_SPCLK    0xFFFF0500 
#define BSP_IO_QSPI0_IO0      0xFFFF0501 
#define BSP_IO_QSPI0_IO1      0xFFFF0502 
#define BSP_IO_QSPI0_SSL      0xFFFF0505 
#define BSP_IO_WDTOVF_PERROUT 0xFFFF0600 
#define BSP_IO_RIIC0_SDA      0xFFFF0700 
#define BSP_IO_RIIC0_SCL      0xFFFF0701 


 
#define RZA_FILNUM_4_STAGE  0 
#define RZA_FILNUM_8_STAGE  1 
#define RZA_FILNUM_12_STAGE 2 
#define RZA_FILNUM_16_STAGE 3 
 
#define RZA_FILCLKSEL_NOT_DIV   0 
#define RZA_FILCLKSEL_DIV_9000  1 
#define RZA_FILCLKSEL_DIV_18000 2 
#define RZA_FILCLKSEL_DIV_36000 3 


#define RZA_FILTER_SET(filnum, filclksel) ((((filnum) & 0x3) << 0x2) | ((filclksel) & 0x3))

 
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZA3M_H_ */