pinctrl-rzg3e.h

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/*
 * Copyright (c) 2025 Renesas Electronics Corporation
 * SPDX-License-Identifier: Apache-2.0
 */

 
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG3E_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG3E_H_


 
#define PORT_00 0x0000 
#define PORT_01 0x0100 
#define PORT_02 0x0200 
#define PORT_03 0x0300 
#define PORT_04 0x0400 
#define PORT_05 0x0500 
#define PORT_06 0x0600 
#define PORT_07 0x0700 
#define PORT_08 0x0800 
#define PORT_10 0x0A00 
#define PORT_11 0x0B00 
#define PORT_12 0x0C00 
#define PORT_13 0x0D00 
#define PORT_14 0x0E00 
#define PORT_15 0x0F00 
#define PORT_16 0x1000 
#define PORT_17 0x1100 
#define PORT_19 0x1300 
#define PORT_20 0x1400 
#define PORT_21 0x1500 
#define PORT_22 0x1600 
#define PORT_28 0x1C00 


 
#define BSP_IO_WDTUDFCA 0xFFFF0500 
#define BSP_IO_WDTUDFCM 0xFFFF0501 
 
#define BSP_IO_SCIF_RXD 0xFFFF0600 
#define BSP_IO_SCIF_TXD 0xFFFF0601 
 
#define BSP_IO_SD0CLK  0xFFFF0900 
#define BSP_IO_SD0CMD  0xFFFF0901 
#define BSP_IO_SD0RSTN 0xFFFF0902 
#define BSP_IO_SD0PWEN 0xFFFF0903 
#define BSP_IO_SD0IOVS 0xFFFF0904 
 
#define BSP_IO_SD0DAT0 0xFFFF0A00 
#define BSP_IO_SD0DAT1 0xFFFF0A01 
#define BSP_IO_SD0DAT2 0xFFFF0A02 
#define BSP_IO_SD0DAT3 0xFFFF0A03 
#define BSP_IO_SD0DAT4 0xFFFF0A04 
#define BSP_IO_SD0DAT5 0xFFFF0A05 
#define BSP_IO_SD0DAT6 0xFFFF0A06 
#define BSP_IO_SD0DAT7 0xFFFF0A07 


 
#define RZG_FILNUM_4_STAGE  0 
#define RZG_FILNUM_8_STAGE  1 
#define RZG_FILNUM_12_STAGE 2 
#define RZG_FILNUM_16_STAGE 3 
 
#define RZG_FILCLKSEL_DIV_4   0 
#define RZG_FILCLKSEL_DIV_32  1 
#define RZG_FILCLKSEL_DIV_128 2 
#define RZG_FILCLKSEL_DIV_256 3 


#define RZG_PINMUX(port, pin, func) (port | pin | ((func) << 4))

#define RZG_FILTER_SET(filnum, filclksel) (((filnum) & 0x3) << 0x2) | (filclksel & 0x3)

 
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG3E_H_ */