r8a779g0_cpg_mssr.h

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/*
 * Copyright (c) 2025 Renesas Electronics Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

 
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779G0_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779G0_H_
 
#include "renesas_cpg_mssr.h"

/* r8a779g0 CPG Core Clocks */
#define R8A779G0_CLK_Z0  0
#define R8A779G0_CLK_Z1  1
#define R8A779G0_CLK_Z2  2
#define R8A779G0_CLK_ZG  3
#define R8A779G0_CLK_ZR  4
#define R8A779G0_CLK_ZX  5
#define R8A779G0_CLK_ZS  6
#define R8A779G0_CLK_ZT  7
#define R8A779G0_CLK_ZTR 8
 
#define R8A779G0_CLK_S0   9
#define R8A779G0_CLK_S0D2 10
#define R8A779G0_CLK_S0D3 11
#define R8A779G0_CLK_S0D4 12
 
#define R8A779G0_CLK_S0VIO    13
#define R8A779G0_CLK_S0D1_VIO 14
#define R8A779G0_CLK_S0D2_VIO 15
#define R8A779G0_CLK_S0D4_VIO 16
#define R8A779G0_CLK_S0D8_VIO 17
 
#define R8A779G0_CLK_S0VC    18
#define R8A779G0_CLK_S0D1_VC 19
#define R8A779G0_CLK_S0D2_VC 20
#define R8A779G0_CLK_S0D4_VC 21
 
#define R8A779G0_CLK_S0D2_MM 22
#define R8A779G0_CLK_S0D4_MM 23
 
#define R8A779G0_CLK_S0D2_U3DG 24
#define R8A779G0_CLK_S0D4_U3DG 25
 
#define R8A779G0_CLK_S0D2_RT  26
#define R8A779G0_CLK_S0D3_RT  27
#define R8A779G0_CLK_S0D4_RT  28
#define R8A779G0_CLK_S0D6_RT  29
#define R8A779G0_CLK_S0D24_RT 30
 
#define R8A779G0_CLK_S0D2_PER  31
#define R8A779G0_CLK_S0D3_PER  32
#define R8A779G0_CLK_S0D4_PER  33
#define R8A779G0_CLK_S0D6_PER  34
#define R8A779G0_CLK_S0D12_PER 35
#define R8A779G0_CLK_S0D24_PER 36
 
#define R8A779G0_CLK_S0_HSC   37
#define R8A779G0_CLK_S0D1_HSC 38
#define R8A779G0_CLK_S0D2_HSC 39
#define R8A779G0_CLK_S0D4_HSC 40
#define R8A779G0_CLK_S0D8_HSC 41
 
#define R8A779G0_CLK_S0D2_CC  42
#define R8A779G0_CLK_SV_IR    43
#define R8A779G0_CLK_SVD1_IR  44
#define R8A779G0_CLK_SVD2_IR  45
#define R8A779G0_CLK_IMPA0    46
#define R8A779G0_CLK_SV_VIP   47
#define R8A779G0_CLK_SVD1_VIP 48
#define R8A779G0_CLK_SVD2_VIP 49
 
#define R8A779G0_CLK_CL        50
#define R8A779G0_CLK_CL16M     51
#define R8A779G0_CLK_CL16M_MM  52
#define R8A779G0_CLK_CL16M_RT  53
#define R8A779G0_CLK_CL16M_PER 54
#define R8A779G0_CLK_CL16M_HSC 55
 
#define R8A779G0_CLK_ZB3   56
#define R8A779G0_CLK_ZB3D2 57
#define R8A779G0_CLK_ZB3D4 58
 
#define R8A779G0_CLK_SDSRC 59
#define R8A779G0_CLK_SD0H  60
#define R8A779G0_CLK_SD0   61
#define R8A779G0_CLK_RPC   62
#define R8A779G0_CLK_RPCD2 63
#define R8A779G0_CLK_MSO   64
#define R8A779G0_CLK_CANFD 65
#define R8A779G0_CLK_CSI   66
#define R8A779G0_CLK_FRAY  67
#define R8A779G0_CLK_IPC   68
#define R8A779G0_CLK_POST2 69
#define R8A779G0_CLK_POST3 70
#define R8A779G0_CLK_POST4 71
#define R8A779G0_CLK_POST  72
 
#define R8A779G0_CLK_SASYNCRT    73
#define R8A779G0_CLK_SASYNCPERD1 74
#define R8A779G0_CLK_SASYNCPERD2 75
#define R8A779G0_CLK_SASYNCPERD4 76
 
#define R8A779G0_CLK_VIOBUS   77
#define R8A779G0_CLK_VIOBUSD2 78
#define R8A779G0_CLK_VCBUS    79
#define R8A779G0_CLK_VCBUSD2  80
#define R8A779G0_CLK_IMPA1    81
#define R8A779G0_CLK_DSIREF   82
#define R8A779G0_CLK_ADGH     83
 
#define R8A779G0_CLK_OSCCLK 84
#define R8A779G0_CLK_IMPA   85
#define R8A779G0_CLK_IMPAD4 86
#define R8A779G0_CLK_CPEX   87
#define R8A779G0_CLK_CP     88
#define R8A779G0_CLK_CBFUSA 89
#define R8A779G0_CLK_RCLK   90
 
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779G0_H_ */