Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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ra_clock.h
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1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_
8#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_
9
10#define RA_PLL_SOURCE_HOCO 0
11#define RA_PLL_SOURCE_MOCO 1
12#define RA_PLL_SOURCE_LOCO 2
13#define RA_PLL_SOURCE_MAIN_OSC 3
14#define RA_PLL_SOURCE_SUBCLOCK 4
15#define RA_PLL_SOURCE_DISABLE 0xff
16
17#define RA_CLOCK_SOURCE_HOCO 0
18#define RA_CLOCK_SOURCE_MOCO 1
19#define RA_CLOCK_SOURCE_LOCO 2
20#define RA_CLOCK_SOURCE_MAIN_OSC 3
21#define RA_CLOCK_SOURCE_SUBCLOCK 4
22#define RA_CLOCK_SOURCE_PLL 5
23#define RA_CLOCK_SOURCE_PLL1P RA_CLOCK_SOURCE_PLL
24#define RA_CLOCK_SOURCE_PLL2 6
25#define RA_CLOCK_SOURCE_PLL2P RA_CLOCK_SOURCE_PLL2
26#define RA_CLOCK_SOURCE_PLL1Q 7
27#define RA_CLOCK_SOURCE_PLL1R 8
28#define RA_CLOCK_SOURCE_PLL2Q 9
29#define RA_CLOCK_SOURCE_PLL2R 10
30#define RA_CLOCK_SOURCE_DISABLE 0xff
31
32#define RA_SYS_CLOCK_DIV_1 0
33#define RA_SYS_CLOCK_DIV_2 1
34#define RA_SYS_CLOCK_DIV_4 2
35#define RA_SYS_CLOCK_DIV_8 3
36#define RA_SYS_CLOCK_DIV_16 4
37#define RA_SYS_CLOCK_DIV_32 5
38#define RA_SYS_CLOCK_DIV_64 6
39#define RA_SYS_CLOCK_DIV_128 7 /* available for CLKOUT only */
40#define RA_SYS_CLOCK_DIV_3 8
41#define RA_SYS_CLOCK_DIV_6 9
42#define RA_SYS_CLOCK_DIV_12 10
43
44/* PLL divider options. */
45#define RA_PLL_DIV_1 0
46#define RA_PLL_DIV_2 1
47#define RA_PLL_DIV_3 2
48#define RA_PLL_DIV_4 3
49#define RA_PLL_DIV_5 4
50#define RA_PLL_DIV_6 5
51#define RA_PLL_DIV_8 7
52#define RA_PLL_DIV_9 8
53#define RA_PLL_DIV_16 15
54
55/* USB clock divider options. */
56#define RA_USB_CLOCK_DIV_1 0
57#define RA_USB_CLOCK_DIV_2 1
58#define RA_USB_CLOCK_DIV_3 2
59#define RA_USB_CLOCK_DIV_4 3
60#define RA_USB_CLOCK_DIV_5 4
61#define RA_USB_CLOCK_DIV_6 5
62#define RA_USB_CLOCK_DIV_8 7
63
64/* USB60 clock divider options. */
65#define RA_USB60_CLOCK_DIV_1 0
66#define RA_USB60_CLOCK_DIV_2 1
67#define RA_USB60_CLOCK_DIV_3 5
68#define RA_USB60_CLOCK_DIV_4 2
69#define RA_USB60_CLOCK_DIV_5 6
70#define RA_USB60_CLOCK_DIV_6 3
71#define RA_USB60_CLOCK_DIV_8 4
72
73/* OCTA clock divider options. */
74#define RA_OCTA_CLOCK_DIV_1 0
75#define RA_OCTA_CLOCK_DIV_2 1
76#define RA_OCTA_CLOCK_DIV_4 2
77#define RA_OCTA_CLOCK_DIV_6 3
78#define RA_OCTA_CLOCK_DIV_8 4
79
80/* CANFD clock divider options. */
81#define RA_CANFD_CLOCK_DIV_1 0
82#define RA_CANFD_CLOCK_DIV_2 1
83#define RA_CANFD_CLOCK_DIV_3 5
84#define RA_CANFD_CLOCK_DIV_4 2
85#define RA_CANFD_CLOCK_DIV_5 6
86#define RA_CANFD_CLOCK_DIV_6 3
87#define RA_CANFD_CLOCK_DIV_8 4
88
89/* SCI clock divider options. */
90#define RA_SCI_CLOCK_DIV_1 0
91#define RA_SCI_CLOCK_DIV_2 1
92#define RA_SCI_CLOCK_DIV_3 5
93#define RA_SCI_CLOCK_DIV_4 2
94#define RA_SCI_CLOCK_DIV_5 6
95#define RA_SCI_CLOCK_DIV_6 3
96#define RA_SCI_CLOCK_DIV_8 4
97
98/* SPI clock divider options. */
99#define RA_SPI_CLOCK_DIV_1 0
100#define RA_SPI_CLOCK_DIV_2 1
101#define RA_SPI_CLOCK_DIV_3 5
102#define RA_SPI_CLOCK_DIV_4 2
103#define RA_SPI_CLOCK_DIV_5 6
104#define RA_SPI_CLOCK_DIV_6 3
105#define RA_SPI_CLOCK_DIV_8 4
106
107/* CEC clock divider options. */
108#define RA_CEC_CLOCK_DIV_1 0
109#define RA_CEC_CLOCK_DIV_2 1
110
111/* I3C clock divider options. */
112#define RA_I3C_CLOCK_DIV_1 0
113#define RA_I3C_CLOCK_DIV_2 1
114#define RA_I3C_CLOCK_DIV_3 5
115#define RA_I3C_CLOCK_DIV_4 2
116#define RA_I3C_CLOCK_DIV_5 6
117#define RA_I3C_CLOCK_DIV_6 3
118#define RA_I3C_CLOCK_DIV_8 4
119
120#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_ */