6#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RX_CGC_H_
7#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RX_CGC_H_
12#define RX_CGC_PROP_HAS_STATUS_OKAY_OR(node_id, prop, default_value) \
13 COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), (DT_PROP(node_id, prop)), (default_value))
15#define RX_CGC_CLK_SRC(node_id) \
16 COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), \
17 (UTIL_CAT(RX_CLOCKS_SOURCE_, DT_NODE_FULL_NAME_UPPER_TOKEN(node_id))), \
18 (RX_CLOCKS_CLOCK_DISABLED))
Public Clock Control APIs.
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
Definition renesas_rx_cgc.h:20
const struct device * clock_src_dev
Definition renesas_rx_cgc.h:21
uint32_t clk_div
Definition renesas_rx_cgc.h:22
Definition renesas_rx_cgc.h:30
const struct device * clock_dev
Definition renesas_rx_cgc.h:31
Definition renesas_rx_cgc.h:34
uint32_t pll_div
Definition renesas_rx_cgc.h:35
uint32_t pll_mul
Definition renesas_rx_cgc.h:36
Definition renesas_rx_cgc.h:39
uint32_t rate
Definition renesas_rx_cgc.h:40
Definition renesas_rx_cgc.h:25
uint32_t stop_bit
Definition renesas_rx_cgc.h:27
uint32_t mstp
Definition renesas_rx_cgc.h:26
Runtime device structure (in ROM) per driver instance.
Definition device.h:510