7#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RZ_CGC_H_
8#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RZ_CGC_H_
12#define RZ_CGC_SUBCLK_DIV(subclk) \
13 UTIL_CAT(RZ_CGC_DIV_, DT_NODE_FULL_NAME_UPPER_TOKEN(subclk)) \
14 (DT_PROP(subclk, div))
16#define RZ_CGC_SUBCLK_MUL(subclk) \
17 UTIL_CAT(RZ_CGC_MUL_, DT_NODE_FULL_NAME_UPPER_TOKEN(subclk)) \
18 (DT_PROP(subclk, mul))
20#define RZ_CGC_DIV_CKIO(n) UTIL_CAT(BSP_CLOCKS_CKIO_ICLK_DIV, n)
21#define RZ_CGC_MUL_CPU0CLK(n) UTIL_CAT(BSP_CLOCKS_FSELCPU0_ICLK_MUL, n)
22#define RZ_CGC_MUL_CPU1CLK(n) UTIL_CAT(BSP_CLOCKS_FSELCPU1_ICLK_MUL, n)
Main header file for clock control driver API.