Zephyr Project API 4.1.99
A Scalable Open Source RTOS
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renesas_rz_dma.h
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1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_RENESAS_RZ_DMA_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_RENESAS_RZ_DMA_H_
8
9/* mode: bit 0 (0: Normal, 1: Block) */
10/* source data size: bit 1, 2, 3 (0b000 -> 0b111) */
11/* dest data size: bit 4, 5, 6 (0b000 -> 0b111) */
12/* source addr mode: bit 7 (0: incremented, 1: fixed) */
13/* dest addr mode: bit 8 (0: incremented, 1: fixed) */
14
15#define RZ_DMA_MODE_NORMAL (0U)
16#define RZ_DMA_MODE_BLOCK (1U)
17
18/* DMA source data size config on bits 1, 2, 3 */
19#define RZ_DMA_CFG_SRC_DATA_SIZE(val) ((val & 0x7) << 1)
20#define RZ_DMA_SRC_1_BYTE RZ_DMA_CFG_SRC_DATA_SIZE(0)
21#define RZ_DMA_SRC_2_BYTE RZ_DMA_CFG_SRC_DATA_SIZE(1)
22#define RZ_DMA_SRC_4_BYTE RZ_DMA_CFG_SRC_DATA_SIZE(2)
23#define RZ_DMA_SRC_8_BYTE RZ_DMA_CFG_SRC_DATA_SIZE(3)
24#define RZ_DMA_SRC_16_BYTE RZ_DMA_CFG_SRC_DATA_SIZE(4)
25#define RZ_DMA_SRC_32_BYTE RZ_DMA_CFG_SRC_DATA_SIZE(5)
26#define RZ_DMA_SRC_64_BYTE RZ_DMA_CFG_SRC_DATA_SIZE(6)
27#define RZ_DMA_SRC_128_BYTE RZ_DMA_CFG_SRC_DATA_SIZE(7)
28
29/* DMA destination data size config on bits 4, 5, 6 */
30#define RZ_DMA_CFG_DEST_DATA_SIZE(val) ((val & 0x7) << 4)
31#define RZ_DMA_DEST_1_BYTE RZ_DMA_CFG_DEST_DATA_SIZE(0)
32#define RZ_DMA_DEST_2_BYTE RZ_DMA_CFG_DEST_DATA_SIZE(1)
33#define RZ_DMA_DEST_4_BYTE RZ_DMA_CFG_DEST_DATA_SIZE(2)
34#define RZ_DMA_DEST_8_BYTE RZ_DMA_CFG_DEST_DATA_SIZE(3)
35#define RZ_DMA_DEST_16_BYTE RZ_DMA_CFG_DEST_DATA_SIZE(4)
36#define RZ_DMA_DEST_32_BYTE RZ_DMA_CFG_DEST_DATA_SIZE(5)
37#define RZ_DMA_DEST_64_BYTE RZ_DMA_CFG_DEST_DATA_SIZE(6)
38#define RZ_DMA_DEST_128_BYTE RZ_DMA_CFG_DEST_DATA_SIZE(7)
39
40/* DMA source address mode config on bit 7 */
41#define RZ_DMA_CFG_SRC_ADDR_MODE(val) ((val & 0x1) << 7)
42#define RZ_DMA_SRC_INCREMENTED RZ_DMA_CFG_SRC_ADDR_MODE(0)
43#define RZ_DMA_SRC_FIXED RZ_DMA_CFG_SRC_ADDR_MODE(1)
44
45/* DMA source address mode config on bit 8 */
46#define RZ_DMA_CFG_DEST_ADDR_MODE(val) ((val & 0x1) << 8)
47#define RZ_DMA_DEST_INCREMENTED RZ_DMA_CFG_DEST_ADDR_MODE(0)
48#define RZ_DMA_DEST_FIXED RZ_DMA_CFG_DEST_ADDR_MODE(1)
49
50/* DMA usual combination for peripheral transfer */
51#define RZ_DMA_MEM_TO_PERIPH \
52 (RZ_DMA_MODE_NORMAL | RZ_DMA_SRC_INCREMENTED | RZ_DMA_DEST_FIXED | RZ_DMA_SRC_1_BYTE | \
53 RZ_DMA_DEST_1_BYTE)
54#define RZ_DMA_PERIPH_TO_MEM \
55 (RZ_DMA_MODE_NORMAL | RZ_DMA_SRC_FIXED | RZ_DMA_DEST_INCREMENTED | RZ_DMA_SRC_1_BYTE | \
56 RZ_DMA_DEST_1_BYTE)
57
58#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_RENESAS_RZ_DMA_H_ */