Zephyr Project API 4.3.99
A Scalable Open Source RTOS
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rtl8752h-pinctrl.h
Go to the documentation of this file.
1/*
2 * Copyright (c) 2026, Realtek Semiconductor Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
14
15#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RTL8752H_PINCTRL_H_
16#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RTL8752H_PINCTRL_H_
17
18#include "bee-pinctrl.h"
19
24#define BEE_IDLE_MODE 0
25#define BEE_UART2_TX 1
26#define BEE_UART2_RX 2
27#define BEE_UART2_CTS 3
28#define BEE_UART2_RTS 4
29#define BEE_I2C0_CLK 5
30#define BEE_I2C0_DAT 6
31#define BEE_I2C1_CLK 7
32#define BEE_I2C1_DAT 8
33#define BEE_PWM2_P 9
34#define BEE_PWM2_N 10
35#define BEE_ENPWM0_P 11
36#define BEE_ENPWM0_N 12
37#define BEE_TIM_PWM0 13
38#define BEE_TIM_PWM1 14
39#define BEE_TIM_PWM2 15
40#define BEE_TIM_PWM3 16
41#define BEE_TIM_PWM4 17
42#define BEE_TIM_PWM5 18
43#define BEE_ENPWM0 19
44#define BEE_ENPWM1 20
45#define BEE_QDEC_PHASE_A_X 21
46#define BEE_QDEC_PHASE_B_X 22
47#define BEE_QDEC_PHASE_A_Y 23
48#define BEE_QDEC_PHASE_B_Y 24
49#define BEE_QDEC_PHASE_A_Z 25
50#define BEE_QDEC_PHASE_B_Z 26
51#define BEE_UART0_TX 29
52#define BEE_UART0_RX 30
53#define BEE_UART0_CTS 31
54#define BEE_UART0_RTS 32
55#define BEE_IRDA_TX 33
56#define BEE_IRDA_RX 34
57#define BEE_UART1_TX 35
58#define BEE_UART1_RX 36
59#define BEE_UART1_CTS 37
60#define BEE_UART1_RTS 38
61#define BEE_SPI1_SS_N_0_MASTER 39
62#define BEE_SPI1_SS_N_1_MASTER 40
63#define BEE_SPI1_SS_N_2_MASTER 41
64#define BEE_SPI1_CLK_MASTER 42
65#define BEE_SPI1_MO_MASTER 43
66#define BEE_SPI1_MI_MASTER 44
67#define BEE_SPI0_SS_N_0_SLAVE 45
68#define BEE_SPI0_CLK_SLAVE 46
69#define BEE_SPI0_SO_SLAVE 47
70#define BEE_SPI0_SI_SLAVE 48
71#define BEE_SPI0_SS_N_0_MASTER 49
72#define BEE_SPI0_CLK_MASTER 50
73#define BEE_SPI0_MO_MASTER 51
74#define BEE_SPI0_MI_MASTER 52
75#define BEE_SPI2W_DATA 53
76#define BEE_SPI2W_CLK 54
77#define BEE_SPI2W_CS 55
78#define BEE_SWD_CLK 56
79#define BEE_SWD_DIO 57
80#define BEE_KEY_COL_0 58
81#define BEE_KEY_COL_1 59
82#define BEE_KEY_COL_2 60
83#define BEE_KEY_COL_3 61
84#define BEE_KEY_COL_4 62
85#define BEE_KEY_COL_5 63
86#define BEE_KEY_COL_6 64
87#define BEE_KEY_COL_7 65
88#define BEE_KEY_COL_8 66
89#define BEE_KEY_COL_9 67
90#define BEE_KEY_COL_10 68
91#define BEE_KEY_COL_11 69
92#define BEE_KEY_COL_12 70
93#define BEE_KEY_COL_13 71
94#define BEE_KEY_COL_14 72
95#define BEE_KEY_COL_15 73
96#define BEE_KEY_COL_16 74
97#define BEE_KEY_COL_17 75
98#define BEE_KEY_COL_18 76
99#define BEE_KEY_COL_19 77
100#define BEE_KEY_ROW_0 78
101#define BEE_KEY_ROW_1 79
102#define BEE_KEY_ROW_2 80
103#define BEE_KEY_ROW_3 81
104#define BEE_KEY_ROW_4 82
105#define BEE_KEY_ROW_5 83
106#define BEE_KEY_ROW_6 84
107#define BEE_KEY_ROW_7 85
108#define BEE_KEY_ROW_8 86
109#define BEE_KEY_ROW_9 87
110#define BEE_KEY_ROW_10 88
111#define BEE_KEY_ROW_11 89
112#define BEE_DWGPIO 90
113#define BEE_DMIC1_CLK 96
114#define BEE_DMIC1_DAT 97
115#define BEE_LRC_I_CODEC_SLAVE 98
116#define BEE_BCLK_I_CODEC_SLAVE 99
117#define BEE_SDI_CODEC_SLAVE 100
118#define BEE_SDO_CODEC_SLAVE 101
119#define BEE_BT_COEX_I_0 106
120#define BEE_BT_COEX_I_1 107
121#define BEE_BT_COEX_I_2 108
122#define BEE_BT_COEX_I_3 109
123#define BEE_BT_COEX_O_0 110
124#define BEE_BT_COEX_O_1 111
125#define BEE_BT_COEX_O_2 112
126#define BEE_BT_COEX_O_3 113
127#define BEE_PTA_I2C_CLK_SLAVE 114
128#define BEE_PTA_I2C_DAT_SLAVE 115
129#define BEE_PTA_I2C_INT_OUT 116
130#define BEE_EN_EXPA 117
131#define BEE_EN_EXLNA 118
132#define BEE_LRC_SPORT0 123
133#define BEE_BCLK_SPORT0 124
134#define BEE_ADCDAT_SPORT0 125
135#define BEE_DACDAT_SPORT0 126
136#define BEE_MCLK 127
137#define BEE_PINMUX_MAX (BEE_MCLK + 1)
138#define BEE_SW_MODE (BEE_PINMUX_MAX + 1)
139#define BEE_PWR_OFF (BEE_PINMUX_MAX + 2)
140#define BEE_PIN_DISCONNECTED BEE_PIN_MSK
142
147#define P0_0 0
148#define P0_1 1
149#define P0_2 2
150/* Note: P0_3 defaults to outputting the Realtek internal log for rtl8752h. */
151#define P0_3 3
152#define P0_4 4
153#define P0_5 5
154#define P0_6 6
155#define P0_7 7
156/* Note: P1_0/P1_1 default to SWD function for rtl8752h. */
157#define P1_0 8
158#define P1_1 9
159#define P1_3 11
160#define P1_4 12
161#define P1_6 14
162#define P1_7 15
163#define P2_0 16
164#define P2_1 17
165#define P2_2 18
166#define P2_3 19
167#define P2_4 20
168#define P2_5 21
169#define P2_6 22
170#define P2_7 23
171#define P3_0 24
172#define P3_1 25
173#define P3_2 26
174#define P3_3 27
175#define P3_4 28
176#define P3_5 29
177#define P3_6 30
178#define P4_0 32
179#define P4_1 33
180#define P4_2 34
181#define P4_3 35
182#define H_0 36
183#define P5_1 37
184#define P5_2 38
185
187
192/* Port 0 */
193#define BEE_PSEL_GPIOA_0_P0_0 BEE_PSEL(DWGPIO, P0_0)
194#define BEE_PSEL_GPIOA_1_P0_1 BEE_PSEL(DWGPIO, P0_1)
195#define BEE_PSEL_GPIOA_2_P0_2 BEE_PSEL(DWGPIO, P0_2)
196/* Note: P0_3 defaults to outputting the Realtek internal log for rtl8752h. */
197#define BEE_PSEL_GPIOA_3_P0_3 BEE_PSEL(DWGPIO, P0_3)
198#define BEE_PSEL_GPIOA_4_P0_4 BEE_PSEL(DWGPIO, P0_4)
199#define BEE_PSEL_GPIOA_5_P0_5 BEE_PSEL(DWGPIO, P0_5)
200#define BEE_PSEL_GPIOA_6_P0_6 BEE_PSEL(DWGPIO, P0_6)
201#define BEE_PSEL_GPIOA_7_P0_7 BEE_PSEL(DWGPIO, P0_7)
202
203/* Port 1 */
204/* Note: P1_0/P1_1 default to SWD function for rtl8752h. */
205#define BEE_PSEL_GPIOA_8_P1_0 BEE_PSEL(DWGPIO, P1_0)
206#define BEE_PSEL_GPIOA_9_P1_1 BEE_PSEL(DWGPIO, P1_1)
207#define BEE_PSEL_GPIOA_11_P1_3 BEE_PSEL(DWGPIO, P1_3)
208#define BEE_PSEL_GPIOA_12_P1_4 BEE_PSEL(DWGPIO, P1_4)
209#define BEE_PSEL_GPIOA_14_P1_6 BEE_PSEL(DWGPIO, P1_6)
210#define BEE_PSEL_GPIOA_15_P1_7 BEE_PSEL(DWGPIO, P1_7)
211
212/* Port 2 */
213#define BEE_PSEL_GPIOA_16_P2_0 BEE_PSEL(DWGPIO, P2_0)
214#define BEE_PSEL_GPIOA_17_P2_1 BEE_PSEL(DWGPIO, P2_1)
215#define BEE_PSEL_GPIOA_18_P2_2 BEE_PSEL(DWGPIO, P2_2)
216#define BEE_PSEL_GPIOA_19_P2_3 BEE_PSEL(DWGPIO, P2_3)
217#define BEE_PSEL_GPIOA_20_P2_4 BEE_PSEL(DWGPIO, P2_4)
218#define BEE_PSEL_GPIOA_21_P2_5 BEE_PSEL(DWGPIO, P2_5)
219#define BEE_PSEL_GPIOA_22_P2_6 BEE_PSEL(DWGPIO, P2_6)
220#define BEE_PSEL_GPIOA_23_P2_7 BEE_PSEL(DWGPIO, P2_7)
221
222/* Port 3 */
223#define BEE_PSEL_GPIOA_24_P3_0 BEE_PSEL(DWGPIO, P3_0)
224#define BEE_PSEL_GPIOA_25_P3_1 BEE_PSEL(DWGPIO, P3_1)
225#define BEE_PSEL_GPIOA_26_P3_2 BEE_PSEL(DWGPIO, P3_2)
226#define BEE_PSEL_GPIOA_27_P3_3 BEE_PSEL(DWGPIO, P3_3)
227#define BEE_PSEL_GPIOA_28_P3_4 BEE_PSEL(DWGPIO, P3_4)
228#define BEE_PSEL_GPIOA_29_P3_5 BEE_PSEL(DWGPIO, P3_5)
229#define BEE_PSEL_GPIOA_30_P3_6 BEE_PSEL(DWGPIO, P3_6)
230
231/* Port 4 */
232#define BEE_PSEL_GPIOA_13_P4_0 BEE_PSEL(DWGPIO, P4_0)
233#define BEE_PSEL_GPIOA_29_P4_1 BEE_PSEL(DWGPIO, P4_1)
234#define BEE_PSEL_GPIOA_30_P4_2 BEE_PSEL(DWGPIO, P4_2)
235#define BEE_PSEL_GPIOA_31_P4_3 BEE_PSEL(DWGPIO, P4_3)
236
237/* Port 5 */
238#define BEE_PSEL_GPIOA_11_P5_1 BEE_PSEL(DWGPIO, P5_1)
239#define BEE_PSEL_GPIOA_12_P5_2 BEE_PSEL(DWGPIO, P5_2)
240
241/* Other Ports (H) */
242#define BEE_PSEL_GPIOA_10_H_0 BEE_PSEL(DWGPIO, H_0)
243
245
246#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RTL8752H_PINCTRL_H_ */
Realtek BEE Pinctrl Devicetree Bindings.