Zephyr Project API 4.1.99
A Scalable Open Source RTOS
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silabs-pinctrl-dbus.h
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1/*
2 * Copyright (c) 2024 Silicon Labs
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_DBUS_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_DBUS_H_
8
9#include <zephyr/dt-bindings/dt-util.h>
10
11/*
12 * Silabs Series 2 DBUS configuration is encoded in a 32-bit bitfield organized as follows:
13 *
14 * 31 : Whether the configuration represents an analog pin
15 * If digital (bit 31 == 0):
16 * 30 : Reserved
17 * 29 : Route register presence (fixed routes have no route register)
18 * 28..24: Route register offset in words from peripheral config (offset of <fun>ROUTE
19 * register in GPIO_<periph>ROUTE_TypeDef)
20 * 23..19: Enable bit (offset into ROUTEEN register for given function)
21 * 18 : Enable bit presence (some inputs are auto-enabled)
22 * 17..8 : Peripheral config offset in words from DBUS base within GPIO (offset of <periph>ROUTE[n]
23 * register in GPIO_TypeDef minus offset of first route register [DBGROUTEPEN, 0x440])
24 * 7..4 : GPIO pin
25 * 3..0 : GPIO port
26 * If analog (bit 31 == 1):
27 * 15..14: Bus selection (A, B, CD)
28 * 13..12: Bus selection (EVEN0, EVEN1, ODD0, ODD1)
29 * 11..8 : Peripheral selection (bit in GPIO_nBUSALLOC bitfield)
30 * 7 ..0 : Reserved
31 */
32
33#define SILABS_PINCTRL_GPIO_PORT_MASK 0x0000000FUL
34#define SILABS_PINCTRL_GPIO_PIN_MASK 0x000000F0UL
35#define SILABS_PINCTRL_PERIPH_BASE_MASK 0x0003FF00UL
36#define SILABS_PINCTRL_HAVE_EN_MASK 0x00040000UL
37#define SILABS_PINCTRL_EN_BIT_MASK 0x00F80000UL
38#define SILABS_PINCTRL_ROUTE_MASK 0x1F000000UL
39#define SILABS_PINCTRL_HAVE_ROUTE_MASK 0x20000000UL
40
41#define SILABS_PINCTRL_ANALOG_MASK 0x80000000UL
42#define SILABS_PINCTRL_ABUS_BUS_MASK 0x0000C000UL
43#define SILABS_PINCTRL_ABUS_PARITY_MASK 0x00003000UL
44#define SILABS_PINCTRL_ABUS_PERIPH_MASK 0x00000F00UL
45
46#define SILABS_PINCTRL_UNUSED 0xFF
47#define SILABS_PINCTRL_ANALOG 0xAA
48
49#define SILABS_DBUS(port, pin, periph_base, en_present, en_bit, route) \
50 (FIELD_PREP(SILABS_PINCTRL_GPIO_PORT_MASK, port) | \
51 FIELD_PREP(SILABS_PINCTRL_GPIO_PIN_MASK, pin) | \
52 FIELD_PREP(SILABS_PINCTRL_PERIPH_BASE_MASK, periph_base) | \
53 FIELD_PREP(SILABS_PINCTRL_HAVE_EN_MASK, en_present) | \
54 FIELD_PREP(SILABS_PINCTRL_EN_BIT_MASK, en_bit) | \
55 FIELD_PREP(SILABS_PINCTRL_ROUTE_MASK, route) | \
56 FIELD_PREP(SILABS_PINCTRL_HAVE_ROUTE_MASK, 1))
57
58#define SILABS_FIXED_ROUTE(port, pin, periph_base, en_bit) \
59 (FIELD_PREP(SILABS_PINCTRL_GPIO_PORT_MASK, port) | \
60 FIELD_PREP(SILABS_PINCTRL_GPIO_PIN_MASK, pin) | \
61 FIELD_PREP(SILABS_PINCTRL_PERIPH_BASE_MASK, periph_base) | \
62 FIELD_PREP(SILABS_PINCTRL_HAVE_EN_MASK, 1) | \
63 FIELD_PREP(SILABS_PINCTRL_EN_BIT_MASK, en_bit) | \
64 FIELD_PREP(SILABS_PINCTRL_HAVE_ROUTE_MASK, 0))
65
66#define SILABS_ABUS(bus, parity, peripheral) \
67 (FIELD_PREP(SILABS_PINCTRL_ANALOG_MASK, 1) | \
68 FIELD_PREP(SILABS_PINCTRL_ABUS_BUS_MASK, bus) | \
69 FIELD_PREP(SILABS_PINCTRL_ABUS_PARITY_MASK, parity) | \
70 FIELD_PREP(SILABS_PINCTRL_ABUS_PERIPH_MASK, peripheral))
71
72#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_DBUS_H_ */