Zephyr Project API 4.0.99
A Scalable Open Source RTOS
Loading...
Searching...
No Matches
silabs-pinctrl-dbus.h
Go to the documentation of this file.
1/*
2 * Copyright (c) 2024 Silicon Labs
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_DBUS_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_DBUS_H_
8
9#include <zephyr/dt-bindings/dt-util.h>
10
11/*
12 * Silabs Series 2 DBUS configuration is encoded in a 32-bit bitfield organized as follows:
13 *
14 * 31 : Whether the configuration represents an analog pin
15 * If digital (bit 31 == 0):
16 * 30..29: Reserved
17 * 28..24: Route register offset in words from peripheral config (offset of <fun>ROUTE
18 * register in GPIO_<periph>ROUTE_TypeDef)
19 * 23..19: Enable bit (offset into ROUTEEN register for given function)
20 * 18 : Enable bit presence (some inputs are auto-enabled)
21 * 17..8 : Peripheral config offset in words from DBUS base within GPIO (offset of <periph>ROUTE[n]
22 * register in GPIO_TypeDef minus offset of first route register [DBGROUTEPEN, 0x440])
23 * 7..4 : GPIO pin
24 * 3..0 : GPIO port
25 * If analog (bit 31 == 1):
26 * 15..14: Bus selection (A, B, CD)
27 * 13..12: Bus selection (EVEN0, EVEN1, ODD0, ODD1)
28 * 11..8 : Peripheral selection (bit in GPIO_nBUSALLOC bitfield)
29 * 7 ..0 : Reserved
30 */
31
32#define SILABS_PINCTRL_GPIO_PORT_MASK 0x0000000FUL
33#define SILABS_PINCTRL_GPIO_PIN_MASK 0x000000F0UL
34#define SILABS_PINCTRL_PERIPH_BASE_MASK 0x0003FF00UL
35#define SILABS_PINCTRL_HAVE_EN_MASK 0x00040000UL
36#define SILABS_PINCTRL_EN_BIT_MASK 0x00F80000UL
37#define SILABS_PINCTRL_ROUTE_MASK 0x1F000000UL
38
39#define SILABS_PINCTRL_ANALOG_MASK 0x80000000UL
40#define SILABS_PINCTRL_ABUS_BUS_MASK 0x0000C000UL
41#define SILABS_PINCTRL_ABUS_PARITY_MASK 0x00003000UL
42#define SILABS_PINCTRL_ABUS_PERIPH_MASK 0x00000F00UL
43
44#define SILABS_PINCTRL_UNUSED 0xFF
45#define SILABS_PINCTRL_ANALOG 0xAA
46
47#define SILABS_DBUS(port, pin, periph_base, en_present, en_bit, route) \
48 (FIELD_PREP(SILABS_PINCTRL_GPIO_PORT_MASK, port) | \
49 FIELD_PREP(SILABS_PINCTRL_GPIO_PIN_MASK, pin) | \
50 FIELD_PREP(SILABS_PINCTRL_PERIPH_BASE_MASK, periph_base) | \
51 FIELD_PREP(SILABS_PINCTRL_HAVE_EN_MASK, en_present) | \
52 FIELD_PREP(SILABS_PINCTRL_EN_BIT_MASK, en_bit) | \
53 FIELD_PREP(SILABS_PINCTRL_ROUTE_MASK, route))
54
55#define SILABS_ABUS(bus, parity, peripheral) \
56 (FIELD_PREP(SILABS_PINCTRL_ANALOG_MASK, 1) | \
57 FIELD_PREP(SILABS_PINCTRL_ABUS_BUS_MASK, bus) | \
58 FIELD_PREP(SILABS_PINCTRL_ABUS_PARITY_MASK, parity) | \
59 FIELD_PREP(SILABS_PINCTRL_ABUS_PERIPH_MASK, peripheral))
60
61#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_DBUS_H_ */