tcpci.h

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/*
 * Copyright 2024 Google LLC
 * SPDX-License-Identifier: Apache-2.0
 */
 
#ifndef ZEPHYR_INCLUDE_USB_C_TCPCI_H_
#define ZEPHYR_INCLUDE_USB_C_TCPCI_H_


#define TCPC_REG_VENDOR_ID 0x0

#define TCPC_REG_PRODUCT_ID 0x2

#define TCPC_REG_BCD_DEV 0x4

#define TCPC_REG_TC_REV            0x6
#define TCPC_REG_TC_REV_MAJOR_MASK GENMASK(7, 4)
#define TCPC_REG_TC_REV_MAJOR(reg) (((reg) & TCPC_REG_TC_REV_MAJOR_MASK) >> 4)
#define TCPC_REG_TC_REV_MINOR_MASK GENMASK(3, 0)
#define TCPC_REG_TC_REV_MINOR(reg) ((reg) & TCPC_REG_TC_REV_MINOR_MASK)

#define TCPC_REG_PD_REV                0x8
#define TCPC_REG_PD_REV_REV_MAJOR_MASK GENMASK(15, 12)
#define TCPC_REG_PD_REV_REV_MAJOR(reg) (((reg) & TCPC_REG_PD_REV_REV_MAJOR_MASK) >> 12)
#define TCPC_REG_PD_REV_REV_MINOR_MASK GENMASK(11, 8)
#define TCPC_REG_PD_REV_REV_MINOR(reg) (((reg) & TCPC_REG_PD_REV_REV_MINOR_MASK) >> 8)
#define TCPC_REG_PD_REV_VER_MAJOR_MASK GENMASK(7, 4)
#define TCPC_REG_PD_REV_VER_MAJOR(reg) (((reg) & TCPC_REG_PD_REV_VER_MAJOR_MASK) >> 4)
#define TCPC_REG_PD_REV_VER_MINOR_MASK GENMASK(3, 0)
#define TCPC_REG_PD_REV_VER_MINOR(reg) ((reg) & TCPC_REG_PD_REV_VER_MINOR_MASK)

#define TCPC_REG_PD_INT_REV                0xa
#define TCPC_REG_PD_INT_REV_REV_MAJOR_MASK GENMASK(15, 12)
#define TCPC_REG_PD_INT_REV_REV_MAJOR(reg) (((reg) & TCPC_REG_PD_INT_REV_REV_MAJOR_MASK) >> 12)
#define TCPC_REG_PD_INT_REV_REV_MINOR_MASK GENMASK(11, 8)
#define TCPC_REG_PD_INT_REV_REV_MINOR(reg) (((reg) & TCPC_REG_PD_INT_REV_REV_MINOR_MASK) >> 8)
#define TCPC_REG_PD_INT_REV_VER_MAJOR_MASK GENMASK(7, 4)
#define TCPC_REG_PD_INT_REV_VER_MAJOR(reg) (((reg) & TCPC_REG_PD_INT_REV_VER_MAJOR_MASK) >> 4)
#define TCPC_REG_PD_INT_REV_VER_MINOR_MASK GENMASK(3, 0)
#define TCPC_REG_PD_INT_REV_VER_MINOR(reg) ((reg) & TCPC_REG_PD_INT_REV_VER_MINOR_MASK)

#define TCPC_REG_ALERT              0x10
#define TCPC_REG_ALERT_NONE         0x0000
#define TCPC_REG_ALERT_MASK_ALL     0xffff
#define TCPC_REG_ALERT_VENDOR_DEF   BIT(15)
#define TCPC_REG_ALERT_ALERT_EXT    BIT(14)
#define TCPC_REG_ALERT_EXT_STATUS   BIT(13)
#define TCPC_REG_ALERT_RX_BEGINNING BIT(12)
#define TCPC_REG_ALERT_VBUS_DISCNCT BIT(11)
#define TCPC_REG_ALERT_RX_BUF_OVF   BIT(10)
#define TCPC_REG_ALERT_FAULT        BIT(9)
#define TCPC_REG_ALERT_V_ALARM_LO   BIT(8)
#define TCPC_REG_ALERT_V_ALARM_HI   BIT(7)
#define TCPC_REG_ALERT_TX_SUCCESS   BIT(6)
#define TCPC_REG_ALERT_TX_DISCARDED BIT(5)
#define TCPC_REG_ALERT_TX_FAILED    BIT(4)
#define TCPC_REG_ALERT_RX_HARD_RST  BIT(3)
#define TCPC_REG_ALERT_RX_STATUS    BIT(2)
#define TCPC_REG_ALERT_POWER_STATUS BIT(1)
#define TCPC_REG_ALERT_CC_STATUS    BIT(0)
#define TCPC_REG_ALERT_TX_COMPLETE                                                                 \
        (TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_TX_FAILED)

#define TCPC_REG_ALERT_MASK 0x12

#define TCPC_REG_POWER_STATUS_MASK 0x14

#define TCPC_REG_FAULT_STATUS_MASK 0x15

#define TCPC_REG_EXT_STATUS_MASK 0x16

#define TCPC_REG_ALERT_EXT_MASK 0x17

#define TCPC_REG_CONFIG_STD_OUTPUT                   0x18
#define TCPC_REG_CONFIG_STD_OUTPUT_HIGH_Z            BIT(7)
#define TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N    BIT(6)
#define TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N      BIT(5)
#define TCPC_REG_CONFIG_STD_OUTPUT_ACTIVE_CABLE      BIT(4)
#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK          (3 << 2)
#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE          (0 << 2)
#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB           (1 << 2)
#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP            (2 << 2)
#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB_DP        (3 << 2)
#define TCPC_REG_CONFIG_STD_OUTPUT_CONN_PRESENT      BIT(1)
#define TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED BIT(0)

#define TCPC_REG_TCPC_CTRL                           0x19
#define TCPC_REG_TCPC_CTRL_SMBUS_PEC                 BIT(7)
#define TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT  BIT(6)
#define TCPC_REG_TCPC_CTRL_WATCHDOG_TIMER            BIT(5)
#define TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL         BIT(4)
#define TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_MASK        GENMASK(3, 2)
#define TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_DISABLED    0
#define TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_EN_ALWAYS   (2 << 2)
#define TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_EN_NO_ALERT (3 << 2)
#define TCPC_REG_TCPC_CTRL_BIST_TEST_MODE            BIT(1)
#define TCPC_REG_TCPC_CTRL_PLUG_ORIENTATION          BIT(0)

#define TCPC_REG_ROLE_CTRL          0x1a
#define TCPC_REG_ROLE_CTRL_DRP_MASK BIT(6)
#define TCPC_REG_ROLE_CTRL_RP_MASK  GENMASK(5, 4)
#define TCPC_REG_ROLE_CTRL_CC2_MASK GENMASK(3, 2)
#define TCPC_REG_ROLE_CTRL_CC1_MASK GENMASK(1, 0)
#define TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2)                                                  \
        ((((drp) << 6) & TCPC_REG_ROLE_CTRL_DRP_MASK) |                                            \
         (((rp) << 4) & TCPC_REG_ROLE_CTRL_RP_MASK) |                                              \
         (((cc2) << 2) & TCPC_REG_ROLE_CTRL_CC2_MASK) | ((cc1) & TCPC_REG_ROLE_CTRL_CC1_MASK))

#define TCPC_REG_ROLE_CTRL_DRP(reg) (((reg) & TCPC_REG_ROLE_CTRL_DRP_MASK) >> 6)
#define TCPC_REG_ROLE_CTRL_RP(reg)  (((reg) & TCPC_REG_ROLE_CTRL_RP_MASK) >> 4)
#define TCPC_REG_ROLE_CTRL_CC2(reg) (((reg) & TCPC_REG_ROLE_CTRL_CC2_MASK) >> 2)
#define TCPC_REG_ROLE_CTRL_CC1(reg) ((reg) & TCPC_REG_ROLE_CTRL_CC1_MASK)

#define TCPC_REG_FAULT_CTRL                      0x1b
#define TCPC_REG_FAULT_CTRL_VBUS_FORCE_OFF       BIT(4)
#define TCPC_REG_FAULT_CTRL_VBUS_DISCHARGE_FAULT BIT(3)
#define TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS   BIT(2)
#define TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS   BIT(1)
#define TCPC_REG_FAULT_CTRL_VCONN_OCP_FAULT_DIS  BIT(0)

#define TCPC_REG_POWER_CTRL                           0x1c
#define TCPC_REG_POWER_CTRL_FRS_ENABLE                BIT(7)
#define TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS      BIT(6)
#define TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS            BIT(5)
#define TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT BIT(4)
#define TCPC_REG_POWER_CTRL_BLEED_DISCHARGE           BIT(3)
#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE           BIT(2)
#define TCPC_REG_POWER_CTRL_VCONN_SUPP                BIT(1)
#define TCPC_REG_POWER_CTRL_VCONN_EN                  BIT(0)

#define TCPC_REG_CC_STATUS                 0x1d
#define TCPC_REG_CC_STATUS_LOOK4CONNECTION BIT(5)
#define TCPC_REG_CC_STATUS_CONNECT_RESULT  BIT(4)
#define TCPC_REG_CC_STATUS_CC2_STATE_MASK  GENMASK(3, 2)
#define TCPC_REG_CC_STATUS_CC2_STATE(reg)  (((reg) & TCPC_REG_CC_STATUS_CC2_STATE_MASK) >> 2)
#define TCPC_REG_CC_STATUS_CC1_STATE_MASK  GENMASK(1, 0)
#define TCPC_REG_CC_STATUS_CC1_STATE(reg)  ((reg) & TCPC_REG_CC_STATUS_CC1_STATE_MASK)

#define TCPC_REG_POWER_STATUS               0x1e
#define TCPC_REG_POWER_STATUS_DEBUG_ACC_CON BIT(7)
#define TCPC_REG_POWER_STATUS_UNINIT        BIT(6)
#define TCPC_REG_POWER_STATUS_SOURCING_HV   BIT(5)
#define TCPC_REG_POWER_STATUS_SOURCING_VBUS BIT(4)
#define TCPC_REG_POWER_STATUS_VBUS_DET      BIT(3)
#define TCPC_REG_POWER_STATUS_VBUS_PRES     BIT(2)
#define TCPC_REG_POWER_STATUS_VCONN_PRES    BIT(1)
#define TCPC_REG_POWER_STATUS_SINKING_VBUS  BIT(0)

#define TCPC_REG_FAULT_STATUS                      0x1f
#define TCPC_REG_FAULT_STATUS_ALL_REGS_RESET       BIT(7)
#define TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS       BIT(6)
#define TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL  BIT(5)
#define TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL BIT(4)
#define TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT    BIT(3)
#define TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE    BIT(2)
#define TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT   BIT(1)
#define TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR    BIT(0)

#define TCPC_REG_EXT_STATUS        0x20
#define TCPC_REG_EXT_STATUS_SAFE0V BIT(0)

#define TCPC_REG_ALERT_EXT               0x21
#define TCPC_REG_ALERT_EXT_TIMER_EXPIRED BIT(2)
#define TCPC_REG_ALERT_EXT_SRC_FRS       BIT(1)
#define TCPC_REG_ALERT_EXT_SNK_FRS       BIT(0)

#define TCPC_REG_COMMAND                     0x23
#define TCPC_REG_COMMAND_WAKE_I2C            0x11
#define TCPC_REG_COMMAND_DISABLE_VBUS_DETECT 0x22
#define TCPC_REG_COMMAND_ENABLE_VBUS_DETECT  0x33
#define TCPC_REG_COMMAND_SNK_CTRL_LOW        0x44
#define TCPC_REG_COMMAND_SNK_CTRL_HIGH       0x55
#define TCPC_REG_COMMAND_SRC_CTRL_LOW        0x66
#define TCPC_REG_COMMAND_SRC_CTRL_DEF        0x77
#define TCPC_REG_COMMAND_SRC_CTRL_HV         0x88
#define TCPC_REG_COMMAND_LOOK4CONNECTION     0x99
#define TCPC_REG_COMMAND_RX_ONE_MORE         0xAA
#define TCPC_REG_COMMAND_SEND_FRS_SIGNAL     0xCC
#define TCPC_REG_COMMAND_RESET_TRANSMIT_BUF  0xDD
#define TCPC_REG_COMMAND_RESET_RECEIVE_BUF   0xEE
#define TCPC_REG_COMMAND_I2CIDLE             0xFF

#define TCPC_REG_DEV_CAP_1                                 0x24
#define TCPC_REG_DEV_CAP_1_VBUS_NONDEFAULT_TARGET          BIT(15)
#define TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING              BIT(14)
#define TCPC_REG_DEV_CAP_1_VBUS_OVP_REPORTING              BIT(13)
#define TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE                 BIT(12)
#define TCPC_REG_DEV_CAP_1_FORCE_DISCHARGE                 BIT(11)
#define TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE      BIT(10)
#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK               GENMASK(9, 8)
#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR(reg)               \
        (((reg) & TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK) >> 8)

#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_DEF             0
#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_1P5_DEF         1
#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF     2
#define TCPC_REG_DEV_CAP_1_POWER_ROLE_MASK                 GENMASK(7, 5)
#define TCPC_REG_DEV_CAP_1_POWER_ROLE(reg)                 \
        (((reg) & TCPC_REG_DEV_CAP_1_POWER_ROLE_MASK) >> 5)

#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_OR_SNK           0
#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC                  1
#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SNK                  2
#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SNK_ACC              3
#define TCPC_REG_DEV_CAP_1_POWER_ROLE_DRP                  4
#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_SNK_DRP_ADPT_CBL 5
#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_SNK_DRP          6
#define TCPC_REG_DEV_CAP_1_ALL_SOP_STAR_MSGS_SUPPORTED     BIT(4)
#define TCPC_REG_DEV_CAP_1_SOURCE_VCONN                    BIT(3)
#define TCPC_REG_DEV_CAP_1_SINK_VBUS                       BIT(2)
#define TCPC_REG_DEV_CAP_1_SOURCE_HV_VBUS                  BIT(1)
#define TCPC_REG_DEV_CAP_1_SOURCE_VBUS                     BIT(0)

#define TCPC_REG_DEV_CAP_2                         0x26
#define TCPC_REG_DEV_CAP_2_CAP_3_SUPPORTED         BIT(15)
#define TCPC_REG_DEV_CAP_2_MSG_DISABLE_DISCONNECT  BIT(14)
#define TCPC_REG_DEV_CAP_2_GENERIC_TIMER           BIT(13)
#define TCPC_REG_DEV_CAP_2_LONG_MSG                BIT(12)
#define TCPC_REG_DEV_CAP_2_SMBUS_PEC               BIT(11)
#define TCPC_REG_DEV_CAP_2_SRC_FRS                 BIT(10)
#define TCPC_REG_DEV_CAP_2_SNK_FRS                 BIT(9)
#define TCPC_REG_DEV_CAP_2_WATCHDOG_TIMER          BIT(8)
#define TCPC_REG_DEV_CAP_2_SNK_DISC_DET            BIT(7)
#define TCPC_REG_DEV_CAP_2_STOP_DISCHARGE_THRESH   BIT(6)
#define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_MASK GENMASK(5, 4)
#define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM(reg)                                                 \
        (((reg) & TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_MASK) >> 4)

#define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_25MV    0
#define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_50MV    1
#define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_100MV   2
#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_MASK GENMASK(3, 1)
#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED(reg)                                              \
        (((reg) & TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_MASK) >> 1)

#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_1_0W     0
#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_1_5W     1
#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_2_0W     2
#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_3_0W     3
#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_4_0W     4
#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_5_0W     5
#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_6_0W     6
#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_EXTERNAL 7
#define TCPC_REG_DEV_CAP_2_VCONN_OVC_FAULT                BIT(0)

#define TCPC_REG_STD_INPUT_CAP                0x28
#define TCPC_REG_STD_INPUT_CAP_SRC_FRS_MASK   GENMASK(4, 3)
#define TCPC_REG_STD_INPUT_CAP_SRC_FRS(reg)   (((reg) & TCPC_REG_STD_INPUT_CAP_SRC_FRS_MASK) >> 3)
#define TCPC_REG_STD_INTPU_CAP_SRC_FRS_NONE   0
#define TCPC_REG_STD_INTPU_CAP_SRC_FRS_INPUT  1
#define TCPC_REG_STD_INTPU_CAP_SRC_FRS_BOTH   2
#define TCPC_REG_STD_INPUT_CAP_EXT_OVP        BIT(2)
#define TCPC_REG_STD_INPUT_CAP_EXT_OCP        BIT(1)
#define TCPC_REG_STD_INPUT_CAP_FORCE_OFF_VBUS BIT(0)

#define TCPC_REG_STD_OUTPUT_CAP                  0x29
#define TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET     BIT(7)
#define TCPC_REG_STD_OUTPUT_CAP_DBG_ACCESSORY    BIT(6)
#define TCPC_REG_STD_OUTPUT_CAP_VBUS_PRESENT_MON BIT(5)
#define TCPC_REG_STD_OUTPUT_CAP_AUDIO_ACCESSORY  BIT(4)
#define TCPC_REG_STD_OUTPUT_CAP_ACTIVE_CABLE     BIT(3)
#define TCPC_REG_STD_OUTPUT_CAP_MUX_CFG_CTRL     BIT(2)
#define TCPC_REG_STD_OUTPUT_CAP_CONN_PRESENT     BIT(1)
#define TCPC_REG_STD_OUTPUT_CAP_CONN_ORIENTATION BIT(0)

#define TCPC_REG_CONFIG_EXT_1                0x2A
#define TCPC_REG_CONFIG_EXT_1_FRS_SNK_DIR    BIT(1)
#define TCPC_REG_CONFIG_EXT_1_STD_IN_SRC_FRS BIT(0)

#define TCPC_REG_GENERIC_TIMER 0x2c

#define TCPC_REG_MSG_HDR_INFO                 0x2e
#define TCPC_REG_MSG_HDR_INFO_CABLE_PLUG      BIT(4)
#define TCPC_REG_MSG_HDR_INFO_DATA_ROLE_MASK  BIT(3)
#define TCPC_REG_MSG_HDR_INFO_DATA_ROLE(reg)  (((reg) & TCPC_REG_MSG_HDR_INFO_DATA_ROLE_MASK) >> 3)
#define TCPC_REG_MSG_HDR_INFO_DATA_ROLE_UFP   0
#define TCPC_REG_MSG_HDR_INFO_DATA_ROLE_DFP   1
#define TCPC_REG_MSG_HDR_INFO_PD_REV_MASK     GENMASK(2, 1)
#define TCPC_REG_MSG_HDR_INFO_PD_REV(reg)     (((reg) & TCPC_REG_MSG_HDR_INFO_PD_REV_MASK) >> 1)
#define TCPC_REG_MSG_HDR_INFO_PD_REV_1_0      0
#define TCPC_REG_MSG_HDR_INFO_PD_REV_2_0      1
#define TCPC_REG_MSG_HDR_INFO_PD_REV_3_0      2
#define TCPC_REG_MSG_HDR_INFO_POWER_ROLE_MASK BIT(0)
#define TCPC_REG_MSG_HDR_INFO_POWER_ROLE(reg) ((reg) & TCPC_REG_MSG_HDR_INFO_POWER_ROLE_MASK)
#define TCPC_REG_MSG_HDR_INFO_POWER_ROLE_SNK  0
#define TCPC_REG_MSG_HDR_INFO_POWER_ROLE_SRC  1
#define TCPC_REG_MSG_HDR_INFO_SET(pd_rev_type, drole, prole)                                       \
        ((drole) << 3 | (pd_rev_type << 1) | (prole))

#define TCPC_REG_MSG_HDR_INFO_ROLES_MASK (TCPC_REG_MSG_HDR_INFO_SET(3, 1, 1))

#define TCPC_REG_RX_DETECT                        0x2f
#define TCPC_REG_RX_DETECT_MSG_DISABLE_DISCONNECT BIT(7)
#define TCPC_REG_RX_DETECT_CABLE_RST              BIT(6)
#define TCPC_REG_RX_DETECT_HRST                   BIT(5)
#define TCPC_REG_RX_DETECT_SOPPP_DBG              BIT(4)
#define TCPC_REG_RX_DETECT_SOPP_DBG               BIT(3)
#define TCPC_REG_RX_DETECT_SOPPP                  BIT(2)
#define TCPC_REG_RX_DETECT_SOPP                   BIT(1)
#define TCPC_REG_RX_DETECT_SOP                    BIT(0)
#define TCPC_REG_RX_DETECT_SOP_HRST_MASK          (TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_HRST)
#define TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK                                                \
        (TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_SOPP | TCPC_REG_RX_DETECT_SOPPP |             \
         TCPC_REG_RX_DETECT_HRST)

#define TCPC_REG_RX_BUFFER 0x30

#define TCPC_REG_TRANSMIT                               0x50
#define TCPC_REG_TRANSMIT_SET_WITH_RETRY(retries, type) ((retries) << 4 | (type))
#define TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type)       (type)
#define TCPC_REG_TRANSMIT_TYPE_SOP                      0
#define TCPC_REG_TRANSMIT_TYPE_SOPP                     1
#define TCPC_REG_TRANSMIT_TYPE_SOPPP                    2
#define TCPC_REG_TRANSMIT_TYPE_SOP_DBG_P                3
#define TCPC_REG_TRANSMIT_TYPE_SOP_DBG_PP               4
#define TCPC_REG_TRANSMIT_TYPE_HRST                     5
#define TCPC_REG_TRANSMIT_TYPE_CABLE_RST                6
#define TCPC_REG_TRANSMIT_TYPE_BIST                     7

#define TCPC_REG_TX_BUFFER 0x51

#define TCPC_REG_VBUS_VOLTAGE                   0x70
#define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT_MASK  GENMASK(9, 0)
#define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT(reg)  ((reg) & TCPC_REG_VBUS_VOLTAGE_MEASUREMENT_MASK)
#define TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR_MASK GENMASK(11, 10)
#define TCPC_REG_VBUS_VOLTAGE_SCALE(reg)                                                           \
        (1 << (((reg) & TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR_MASK) >> 10))

#define TCPC_REG_VBUS_VOLTAGE_LSB 25
#define TCPC_REG_VBUS_VOLTAGE_VBUS(x)                                                              \
        (TCPC_REG_VBUS_VOLTAGE_SCALE(x) * TCPC_REG_VBUS_VOLTAGE_MEASUREMENT(x) *                   \
         TCPC_REG_VBUS_VOLTAGE_LSB)

#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH         0x72
#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_LSB     25
#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_MASK    GENMASK(11, 0)
#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT 0x008C /* 3.5 V */

#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH         0x74
#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_LSB     25
#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_MASK    GENMASK(11, 0)
#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_DEFAULT 0x0020 /* 0.8 V */

#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG      0x76
#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG_LSB  25
#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG_MASK GENMASK(11, 0)

#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG      0x78
#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG_LSB  25
#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG_MASK GENMASK(11, 0)

#define TCPC_REG_VBUS_NONDEFAULT_TARGET     0x7a
#define TCPC_REG_VBUS_NONDEFAULT_TARGET_LSB 20

#define TCPC_REG_DEV_CAP_3               0x7c
#define TCPC_REG_DEV_CAP_3_VBUS_MAX_MASK GENMASK(2, 0)
#define TCPC_REG_DEV_CAP_3_VBUS_MAX(reg) ((reg) & TCPC_REG_DEV_CAP_3_VBUS_MAX_MASK)
#define TCPC_REG_DEV_CAP_3_VBUS_MAX_5V   0
#define TCPC_REG_DEV_CAP_3_VBUS_MAX_9V   1
#define TCPC_REG_DEV_CAP_3_VBUS_MAX_15V  2
#define TCPC_REG_DEV_CAP_3_VBUS_MAX_20V  3
#define TCPC_REG_DEV_CAP_3_VBUS_MAX_28V  4
#define TCPC_REG_DEV_CAP_3_VBUS_MAX_36V  5
#define TCPC_REG_DEV_CAP_3_VBUS_MAX_48V  6
 
#endif /* ZEPHYR_INCLUDE_USB_C_TCPCI_H_ */