Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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ti_dmtimer.h
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1/* Copyright (C) 2023 BeagleBoard.org Foundation
2 * Copyright (C) 2023 S Prashanth
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#ifndef ZEPHYR_DRIVERS_TIMERS_TI_DMTIMER_H_
8#define ZEPHYR_DRIVERS_TIMERS_TI_DMTIMER_H_
9
10#include <zephyr/devicetree.h>
11
12#define TI_DM_TIMER_TIDR (0x00)
13#define TI_DM_TIMER_TIOCP_CFG (0x10)
14#define TI_DM_TIMER_IRQ_EOI (0x20)
15#define TI_DM_TIMER_IRQSTATUS_RAW (0x24)
16#define TI_DM_TIMER_IRQSTATUS (0x28) /* Interrupt status register */
17#define TI_DM_TIMER_IRQENABLE_SET (0x2c) /* Interrupt enable register */
18#define TI_DM_TIMER_IRQENABLE_CLR (0x30) /* Interrupt disable register */
19#define TI_DM_TIMER_IRQWAKEEN (0x34)
20#define TI_DM_TIMER_TCLR (0x38) /* Control register */
21#define TI_DM_TIMER_TCRR (0x3c) /* Counter register */
22#define TI_DM_TIMER_TLDR (0x40) /* Load register */
23#define TI_DM_TIMER_TTGR (0x44)
24#define TI_DM_TIMER_TWPS (0x48)
25#define TI_DM_TIMER_TMAR (0x4c) /* Match register */
26#define TI_DM_TIMER_TCAR1 (0x50)
27#define TI_DM_TIMER_TSICR (0x54)
28#define TI_DM_TIMER_TCAR2 (0x58)
29#define TI_DM_TIMER_TPIR (0x5c)
30#define TI_DM_TIMER_TNIR (0x60)
31#define TI_DM_TIMER_TCVR (0x64)
32#define TI_DM_TIMER_TOCR (0x68)
33#define TI_DM_TIMER_TOWR (0x6c)
34
35#define TI_DM_TIMER_IRQSTATUS_MAT_IT_FLAG_SHIFT (0)
36#define TI_DM_TIMER_IRQSTATUS_MAT_IT_FLAG_MASK (0x00000001)
37
38#define TI_DM_TIMER_IRQSTATUS_OVF_IT_FLAG_SHIFT (1)
39#define TI_DM_TIMER_IRQSTATUS_OVF_IT_FLAG_MASK (0x00000002)
40
41#define TI_DM_TIMER_IRQSTATUS_TCAR_IT_FLAG_SHIFT (2)
42#define TI_DM_TIMER_IRQSTATUS_TCAR_IT_FLAG_MASK (0x00000004)
43
44#define TI_DM_TIMER_IRQENABLE_SET_MAT_EN_FLAG_SHIFT (0)
45#define TI_DM_TIMER_IRQENABLE_SET_MAT_EN_FLAG_MASK (0x00000001)
46
47#define TI_DM_TIMER_IRQENABLE_SET_OVF_EN_FLAG_SHIFT (1)
48#define TI_DM_TIMER_IRQENABLE_SET_OVF_EN_FLAG_MASK (0x00000002)
49
50#define TI_DM_TIMER_IRQENABLE_SET_TCAR_EN_FLAG_SHIFT (2)
51#define TI_DM_TIMER_IRQENABLE_SET_TCAR_EN_FLAG_MASK (0x00000004)
52
53#define TI_DM_TIMER_IRQENABLE_CLR_MAT_EN_FLAG_SHIFT (0)
54#define TI_DM_TIMER_IRQENABLE_CLR_MAT_EN_FLAG_MASK (0x00000001)
55
56#define TI_DM_TIMER_IRQENABLE_CLR_OVF_EN_FLAG_SHIFT (1)
57#define TI_DM_TIMER_IRQENABLE_CLR_OVF_EN_FLAG_MASK (0x00000002)
58
59#define TI_DM_TIMER_IRQENABLE_CLR_TCAR_EN_FLAG_SHIFT (2)
60#define TI_DM_TIMER_IRQENABLE_CLR_TCAR_EN_FLAG_MASK (0x00000004)
61
62#define TI_DM_TIMER_TCLR_ST_SHIFT (0)
63#define TI_DM_TIMER_TCLR_ST_MASK (0x00000001)
64
65#define TI_DM_TIMER_TCLR_AR_SHIFT (1)
66#define TI_DM_TIMER_TCLR_AR_MASK (0x00000002)
67
68#define TI_DM_TIMER_TCLR_PTV_SHIFT (2)
69#define TI_DM_TIMER_TCLR_PTV_MASK (0x0000001c)
70
71#define TI_DM_TIMER_TCLR_PRE_SHIFT (5)
72#define TI_DM_TIMER_TCLR_PRE_MASK (0x00000020)
73
74#define TI_DM_TIMER_TCLR_CE_SHIFT (6)
75#define TI_DM_TIMER_TCLR_CE_MASK (0x00000040)
76
77#define TI_DM_TIMER_TCLR_SCPWM_SHIFT (7)
78#define TI_DM_TIMER_TCLR_SCPWM_MASK (0x00000080)
79
80#define TI_DM_TIMER_TCLR_TCM_SHIFT (8)
81#define TI_DM_TIMER_TCLR_TCM_MASK (0x00000300)
82
83#define TI_DM_TIMER_TCLR_TRG_SHIFT (10)
84#define TI_DM_TIMER_TCLR_TRG_MASK (0x00000c00)
85
86#define TI_DM_TIMER_TCLR_PT_SHIFT (12)
87#define TI_DM_TIMER_TCLR_PT_MASK (0x00001000)
88
89#define TI_DM_TIMER_TCLR_CAPT_MODE_SHIFT (13)
90#define TI_DM_TIMER_TCLR_CAPT_MODE_MASK (0x00002000)
91
92#define TI_DM_TIMER_TCLR_GPO_CFG_SHIFT (14)
93#define TI_DM_TIMER_TCLR_GPO_CFG_MASK (0x00004000)
94
95#define TI_DM_TIMER_TCRR_TIMER_COUNTER_SHIFT (0)
96#define TI_DM_TIMER_TCRR_TIMER_COUNTER_MASK (0xffffffff)
97
98#define TI_DM_TIMER_TLDR_LOAD_VALUE_SHIFT (0)
99#define TI_DM_TIMER_TLDR_LOAD_VALUE_MASK (0xffffffff)
100
101#define TI_DM_TIMER_TMAR_COMPARE_VALUE_SHIFT (0)
102#define TI_DM_TIMER_TMAR_COMPARE_VALUE_MASK (0xffffffff)
103
104#endif /* ZEPHYR_DRIVERS_TIMERS_TI_DMTIMER_H_ */
Devicetree main header.