Zephyr Project API 4.1.99
A Scalable Open Source RTOS
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arch.h
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1/*
2 * Copyright (c) 2019 Intel Corp.
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
14#ifndef ZEPHYR_INCLUDE_ARCH_X86_INTEL64_ARCH_H_
15#define ZEPHYR_INCLUDE_ARCH_X86_INTEL64_ARCH_H_
16
20#if defined(CONFIG_PCIE) && !defined(_ASMLANGUAGE)
22#endif
23
24#if CONFIG_ISR_STACK_SIZE != (CONFIG_ISR_SUBSTACK_SIZE * CONFIG_ISR_DEPTH)
25#error "Check ISR stack configuration (CONFIG_ISR_*)"
26#endif
27
28#if CONFIG_ISR_SUBSTACK_SIZE % ARCH_STACK_PTR_ALIGN
29#error "CONFIG_ISR_SUBSTACK_SIZE must be a multiple of 16"
30#endif
31
32#ifndef _ASMLANGUAGE
33
35{
36 __asm__ volatile("movq %0, %1"
37 :
38 : "r"(data), "m" (*(volatile uint64_t *)
39 (uintptr_t) addr)
40 : "memory");
41}
42
44{
45 uint64_t ret;
46
47 __asm__ volatile("movq %1, %0"
48 : "=r"(ret)
49 : "m" (*(volatile uint64_t *)(uintptr_t) addr)
50 : "memory");
51
52 return ret;
53}
54
55static ALWAYS_INLINE unsigned int arch_irq_lock(void)
56{
57 unsigned long key;
58
59 __asm__ volatile ("pushfq; cli; popq %0" : "=g" (key) : : "memory");
60
61 return (unsigned int) key;
62}
63
64#define ARCH_EXCEPT(reason_p) do { \
65 __asm__ volatile( \
66 "movq %[reason], %%rax\n\t" \
67 "int $32\n\t" \
68 : \
69 : [reason] "i" (reason_p)); \
70 CODE_UNREACHABLE; /* LCOV_EXCL_LINE */ \
71} while (false)
72
73#ifdef CONFIG_PCIE
74#define X86_RESERVE_IRQ(irq_p, name) \
75 static TYPE_SECTION_ITERABLE(uint8_t, name, irq_alloc, name) = irq_p
76#else
77#define X86_RESERVE_IRQ(irq_p, name)
78#endif
79
80#endif /* _ASMLANGUAGE */
81
82/*
83 * All Intel64 interrupts are dynamically connected.
84 */
85
86#define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
87 X86_RESERVE_IRQ(irq_p, _CONCAT(_irq_alloc_fixed, __COUNTER__)); \
88 arch_irq_connect_dynamic(irq_p, priority_p, \
89 (void (*)(const void *))isr_p, \
90 isr_param_p, flags_p)
91
92#ifdef CONFIG_PCIE
93
94#define ARCH_PCIE_IRQ_CONNECT(bdf_p, irq_p, priority_p, \
95 isr_p, isr_param_p, flags_p) \
96 X86_RESERVE_IRQ(irq_p, _CONCAT(_irq_alloc_fixed, __COUNTER__)); \
97 pcie_connect_dynamic_irq(bdf_p, irq_p, priority_p, \
98 (void (*)(const void *))isr_p, \
99 isr_param_p, flags_p)
100
101#endif /* CONFIG_PCIE */
102
103/*
104 * Thread object needs to be 16-byte aligned.
105 */
106#define ARCH_DYNAMIC_OBJ_K_THREAD_ALIGNMENT 16
107
108#endif /* ZEPHYR_INCLUDE_ARCH_X86_INTEL64_ARCH_H_ */
#define ALWAYS_INLINE
Definition common.h:160
static ALWAYS_INLINE unsigned int arch_irq_lock(void)
Definition arch.h:72
__UINT64_TYPE__ uint64_t
Definition stdint.h:91
__UINTPTR_TYPE__ uintptr_t
Definition stdint.h:105
uintptr_t mm_reg_t
Definition sys_io.h:20
static ALWAYS_INLINE uint64_t sys_read64(mm_reg_t addr)
Definition arch.h:43
static ALWAYS_INLINE void sys_write64(uint64_t data, mm_reg_t addr)
Definition arch.h:34