Zephyr Project API
4.1.99
A Scalable Open Source RTOS
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xg27-pinctrl.h
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/*
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* Copyright (c) 2025 Silicon Laboratories Inc.
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* SPDX-License-Identifier: Apache-2.0
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*
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* Pin Control for Silicon Labs XG27 devices
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*
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* This file was generated by the script gen_pinctrl.py in the hal_silabs module.
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* Do not manually edit.
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*/
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#ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG27_PINCTRL_H_
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#define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG27_PINCTRL_H_
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#include <
dt-bindings/pinctrl/silabs-pinctrl-dbus.h
>
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#define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
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#define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 2)
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#define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 7, 1, 1, 3)
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#define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 7, 1, 2, 4)
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#define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 7, 0, 0, 1)
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#define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1)
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#define SILABS_DBUS_EUSART0_RTS(port, pin) SILABS_DBUS(port, pin, 19, 1, 1, 3)
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#define SILABS_DBUS_EUSART0_RX(port, pin) SILABS_DBUS(port, pin, 19, 1, 2, 4)
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#define SILABS_DBUS_EUSART0_SCLK(port, pin) SILABS_DBUS(port, pin, 19, 1, 3, 5)
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#define SILABS_DBUS_EUSART0_TX(port, pin) SILABS_DBUS(port, pin, 19, 1, 4, 6)
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#define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 19, 0, 0, 2)
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#define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 27, 1, 0, 1)
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#define SILABS_DBUS_PTI_DFRAME(port, pin) SILABS_DBUS(port, pin, 27, 1, 1, 2)
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#define SILABS_DBUS_PTI_DOUT(port, pin) SILABS_DBUS(port, pin, 27, 1, 2, 3)
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#define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 32, 1, 0, 1)
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#define SILABS_DBUS_I2C0_SDA(port, pin) SILABS_DBUS(port, pin, 32, 1, 1, 2)
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#define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 36, 1, 0, 1)
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#define SILABS_DBUS_I2C1_SDA(port, pin) SILABS_DBUS(port, pin, 36, 1, 1, 2)
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#define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 40, 1, 0, 1)
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#define SILABS_DBUS_LETIMER0_OUT1(port, pin) SILABS_DBUS(port, pin, 40, 1, 1, 2)
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#define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 44, 1, 0, 1)
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#define SILABS_DBUS_MODEM_ANT1(port, pin) SILABS_DBUS(port, pin, 44, 1, 1, 2)
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#define SILABS_DBUS_MODEM_ANTROLLOVER(port, pin) SILABS_DBUS(port, pin, 44, 1, 2, 3)
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#define SILABS_DBUS_MODEM_ANTRR0(port, pin) SILABS_DBUS(port, pin, 44, 1, 3, 4)
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#define SILABS_DBUS_MODEM_ANTRR1(port, pin) SILABS_DBUS(port, pin, 44, 1, 4, 5)
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#define SILABS_DBUS_MODEM_ANTRR2(port, pin) SILABS_DBUS(port, pin, 44, 1, 5, 6)
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#define SILABS_DBUS_MODEM_ANTRR3(port, pin) SILABS_DBUS(port, pin, 44, 1, 6, 7)
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#define SILABS_DBUS_MODEM_ANTRR4(port, pin) SILABS_DBUS(port, pin, 44, 1, 7, 8)
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#define SILABS_DBUS_MODEM_ANTRR5(port, pin) SILABS_DBUS(port, pin, 44, 1, 8, 9)
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#define SILABS_DBUS_MODEM_ANTSWEN(port, pin) SILABS_DBUS(port, pin, 44, 1, 9, 10)
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#define SILABS_DBUS_MODEM_ANTSWUS(port, pin) SILABS_DBUS(port, pin, 44, 1, 10, 11)
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#define SILABS_DBUS_MODEM_ANTTRIG(port, pin) SILABS_DBUS(port, pin, 44, 1, 11, 12)
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#define SILABS_DBUS_MODEM_ANTTRIGSTOP(port, pin) SILABS_DBUS(port, pin, 44, 1, 12, 13)
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#define SILABS_DBUS_MODEM_DCLK(port, pin) SILABS_DBUS(port, pin, 44, 1, 13, 14)
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#define SILABS_DBUS_MODEM_DOUT(port, pin) SILABS_DBUS(port, pin, 44, 1, 14, 16)
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#define SILABS_DBUS_MODEM_DIN(port, pin) SILABS_DBUS(port, pin, 44, 0, 0, 15)
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#define SILABS_DBUS_PDM_CLK(port, pin) SILABS_DBUS(port, pin, 62, 1, 0, 1)
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#define SILABS_DBUS_PDM_DAT0(port, pin) SILABS_DBUS(port, pin, 62, 0, 0, 2)
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#define SILABS_DBUS_PDM_DAT1(port, pin) SILABS_DBUS(port, pin, 62, 0, 0, 3)
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#define SILABS_DBUS_PRS0_ASYNCH0(port, pin) SILABS_DBUS(port, pin, 67, 1, 0, 1)
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#define SILABS_DBUS_PRS0_ASYNCH1(port, pin) SILABS_DBUS(port, pin, 67, 1, 1, 2)
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#define SILABS_DBUS_PRS0_ASYNCH2(port, pin) SILABS_DBUS(port, pin, 67, 1, 2, 3)
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#define SILABS_DBUS_PRS0_ASYNCH3(port, pin) SILABS_DBUS(port, pin, 67, 1, 3, 4)
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#define SILABS_DBUS_PRS0_ASYNCH4(port, pin) SILABS_DBUS(port, pin, 67, 1, 4, 5)
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#define SILABS_DBUS_PRS0_ASYNCH5(port, pin) SILABS_DBUS(port, pin, 67, 1, 5, 6)
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#define SILABS_DBUS_PRS0_ASYNCH6(port, pin) SILABS_DBUS(port, pin, 67, 1, 6, 7)
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#define SILABS_DBUS_PRS0_ASYNCH7(port, pin) SILABS_DBUS(port, pin, 67, 1, 7, 8)
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#define SILABS_DBUS_PRS0_ASYNCH8(port, pin) SILABS_DBUS(port, pin, 67, 1, 8, 9)
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#define SILABS_DBUS_PRS0_ASYNCH9(port, pin) SILABS_DBUS(port, pin, 67, 1, 9, 10)
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#define SILABS_DBUS_PRS0_ASYNCH10(port, pin) SILABS_DBUS(port, pin, 67, 1, 10, 11)
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#define SILABS_DBUS_PRS0_ASYNCH11(port, pin) SILABS_DBUS(port, pin, 67, 1, 11, 12)
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#define SILABS_DBUS_PRS0_SYNCH0(port, pin) SILABS_DBUS(port, pin, 67, 1, 12, 13)
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#define SILABS_DBUS_PRS0_SYNCH1(port, pin) SILABS_DBUS(port, pin, 67, 1, 13, 14)
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#define SILABS_DBUS_PRS0_SYNCH2(port, pin) SILABS_DBUS(port, pin, 67, 1, 14, 15)
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#define SILABS_DBUS_PRS0_SYNCH3(port, pin) SILABS_DBUS(port, pin, 67, 1, 15, 16)
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#define SILABS_DBUS_TIMER0_CC0(port, pin) SILABS_DBUS(port, pin, 85, 1, 0, 1)
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#define SILABS_DBUS_TIMER0_CC1(port, pin) SILABS_DBUS(port, pin, 85, 1, 1, 2)
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#define SILABS_DBUS_TIMER0_CC2(port, pin) SILABS_DBUS(port, pin, 85, 1, 2, 3)
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#define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 85, 1, 3, 4)
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#define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 85, 1, 4, 5)
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#define SILABS_DBUS_TIMER0_CDTI2(port, pin) SILABS_DBUS(port, pin, 85, 1, 5, 6)
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#define SILABS_DBUS_TIMER1_CC0(port, pin) SILABS_DBUS(port, pin, 93, 1, 0, 1)
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#define SILABS_DBUS_TIMER1_CC1(port, pin) SILABS_DBUS(port, pin, 93, 1, 1, 2)
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#define SILABS_DBUS_TIMER1_CC2(port, pin) SILABS_DBUS(port, pin, 93, 1, 2, 3)
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#define SILABS_DBUS_TIMER1_CDTI0(port, pin) SILABS_DBUS(port, pin, 93, 1, 3, 4)
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#define SILABS_DBUS_TIMER1_CDTI1(port, pin) SILABS_DBUS(port, pin, 93, 1, 4, 5)
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#define SILABS_DBUS_TIMER1_CDTI2(port, pin) SILABS_DBUS(port, pin, 93, 1, 5, 6)
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#define SILABS_DBUS_TIMER2_CC0(port, pin) SILABS_DBUS(port, pin, 101, 1, 0, 1)
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#define SILABS_DBUS_TIMER2_CC1(port, pin) SILABS_DBUS(port, pin, 101, 1, 1, 2)
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#define SILABS_DBUS_TIMER2_CC2(port, pin) SILABS_DBUS(port, pin, 101, 1, 2, 3)
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#define SILABS_DBUS_TIMER2_CDTI0(port, pin) SILABS_DBUS(port, pin, 101, 1, 3, 4)
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#define SILABS_DBUS_TIMER2_CDTI1(port, pin) SILABS_DBUS(port, pin, 101, 1, 4, 5)
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#define SILABS_DBUS_TIMER2_CDTI2(port, pin) SILABS_DBUS(port, pin, 101, 1, 5, 6)
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#define SILABS_DBUS_TIMER3_CC0(port, pin) SILABS_DBUS(port, pin, 109, 1, 0, 1)
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#define SILABS_DBUS_TIMER3_CC1(port, pin) SILABS_DBUS(port, pin, 109, 1, 1, 2)
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#define SILABS_DBUS_TIMER3_CC2(port, pin) SILABS_DBUS(port, pin, 109, 1, 2, 3)
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#define SILABS_DBUS_TIMER3_CDTI0(port, pin) SILABS_DBUS(port, pin, 109, 1, 3, 4)
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#define SILABS_DBUS_TIMER3_CDTI1(port, pin) SILABS_DBUS(port, pin, 109, 1, 4, 5)
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#define SILABS_DBUS_TIMER3_CDTI2(port, pin) SILABS_DBUS(port, pin, 109, 1, 5, 6)
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#define SILABS_DBUS_TIMER4_CC0(port, pin) SILABS_DBUS(port, pin, 117, 1, 0, 1)
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#define SILABS_DBUS_TIMER4_CC1(port, pin) SILABS_DBUS(port, pin, 117, 1, 1, 2)
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#define SILABS_DBUS_TIMER4_CC2(port, pin) SILABS_DBUS(port, pin, 117, 1, 2, 3)
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#define SILABS_DBUS_TIMER4_CDTI0(port, pin) SILABS_DBUS(port, pin, 117, 1, 3, 4)
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#define SILABS_DBUS_TIMER4_CDTI1(port, pin) SILABS_DBUS(port, pin, 117, 1, 4, 5)
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#define SILABS_DBUS_TIMER4_CDTI2(port, pin) SILABS_DBUS(port, pin, 117, 1, 5, 6)
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#define SILABS_DBUS_USART0_CS(port, pin) SILABS_DBUS(port, pin, 125, 1, 0, 1)
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#define SILABS_DBUS_USART0_RTS(port, pin) SILABS_DBUS(port, pin, 125, 1, 1, 3)
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#define SILABS_DBUS_USART0_RX(port, pin) SILABS_DBUS(port, pin, 125, 1, 2, 4)
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#define SILABS_DBUS_USART0_CLK(port, pin) SILABS_DBUS(port, pin, 125, 1, 3, 5)
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#define SILABS_DBUS_USART0_TX(port, pin) SILABS_DBUS(port, pin, 125, 1, 4, 6)
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#define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 125, 0, 0, 2)
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#define SILABS_DBUS_USART1_CS(port, pin) SILABS_DBUS(port, pin, 133, 1, 0, 1)
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#define SILABS_DBUS_USART1_RTS(port, pin) SILABS_DBUS(port, pin, 133, 1, 1, 3)
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#define SILABS_DBUS_USART1_RX(port, pin) SILABS_DBUS(port, pin, 133, 1, 2, 4)
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#define SILABS_DBUS_USART1_CLK(port, pin) SILABS_DBUS(port, pin, 133, 1, 3, 5)
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#define SILABS_DBUS_USART1_TX(port, pin) SILABS_DBUS(port, pin, 133, 1, 4, 6)
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#define SILABS_DBUS_USART1_CTS(port, pin) SILABS_DBUS(port, pin, 133, 0, 0, 2)
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#define GPIO_SWCLKTCK_PA1 SILABS_FIXED_ROUTE(0x0, 0x1, 0, 0)
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#define GPIO_SWDIOTMS_PA2 SILABS_FIXED_ROUTE(0x0, 0x2, 0, 1)
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#define GPIO_TDO_PA3 SILABS_FIXED_ROUTE(0x0, 0x3, 0, 2)
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#define GPIO_TDI_PA4 SILABS_FIXED_ROUTE(0x0, 0x4, 0, 3)
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#define GPIO_SWV_PA3 SILABS_FIXED_ROUTE(0x0, 0x3, 1, 0)
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#define GPIO_TRACECLK_PA4 SILABS_FIXED_ROUTE(0x0, 0x4, 1, 1)
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#define GPIO_TRACEDATA0_PA3 SILABS_FIXED_ROUTE(0x0, 0x3, 1, 2)
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#define GPIO_TRACEDATA1_PA5 SILABS_FIXED_ROUTE(0x0, 0x5, 1, 3)
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#define GPIO_TRACEDATA2_PA6 SILABS_FIXED_ROUTE(0x0, 0x6, 1, 4)
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#define GPIO_TRACEDATA3_PA7 SILABS_FIXED_ROUTE(0x0, 0x7, 1, 5)
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#define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0)
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#define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1)
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#define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
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#define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3)
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#define ACMP0_ACMPOUT_PA4 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x4)
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#define ACMP0_ACMPOUT_PA5 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x5)
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#define ACMP0_ACMPOUT_PA6 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x6)
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#define ACMP0_ACMPOUT_PA7 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x7)
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#define ACMP0_ACMPOUT_PA8 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x8)
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#define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0)
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#define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1)
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#define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2)
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#define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3)
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#define ACMP0_ACMPOUT_PB4 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x4)
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#define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0)
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#define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
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#define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2)
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#define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
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#define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4)
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#define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5)
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#define ACMP0_ACMPOUT_PC6 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x6)
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#define ACMP0_ACMPOUT_PC7 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x7)
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#define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0)
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#define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1)
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#define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2)
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#define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3)
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#define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0)
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#define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1)
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#define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2)
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#define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3)
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#define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4)
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#define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5)
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#define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6)
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#define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7)
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#define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0)
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#define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1)
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#define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2)
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#define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3)
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#define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0)
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#define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1)
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#define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2)
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#define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3)
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#define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4)
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#define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5)
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#define CMU_CLKOUT1_PC6 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x6)
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#define CMU_CLKOUT1_PC7 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x7)
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#define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0)
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#define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1)
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#define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2)
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#define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3)
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#define CMU_CLKOUT2_PA0 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x0)
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#define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1)
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#define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2)
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#define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3)
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#define CMU_CLKOUT2_PA4 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x4)
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#define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5)
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#define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6)
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#define CMU_CLKOUT2_PA7 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x7)
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#define CMU_CLKOUT2_PA8 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x8)
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#define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0)
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#define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1)
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#define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2)
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#define CMU_CLKOUT2_PB3 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x3)
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#define CMU_CLKOUT2_PB4 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x4)
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#define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0)
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#define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1)
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#define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2)
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#define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3)
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#define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4)
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#define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5)
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#define CMU_CLKIN0_PC6 SILABS_DBUS_CMU_CLKIN0(0x2, 0x6)
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#define CMU_CLKIN0_PC7 SILABS_DBUS_CMU_CLKIN0(0x2, 0x7)
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#define CMU_CLKIN0_PD0 SILABS_DBUS_CMU_CLKIN0(0x3, 0x0)
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#define CMU_CLKIN0_PD1 SILABS_DBUS_CMU_CLKIN0(0x3, 0x1)
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#define CMU_CLKIN0_PD2 SILABS_DBUS_CMU_CLKIN0(0x3, 0x2)
217
#define CMU_CLKIN0_PD3 SILABS_DBUS_CMU_CLKIN0(0x3, 0x3)
218
219
#define EUSART0_CS_PA0 SILABS_DBUS_EUSART0_CS(0x0, 0x0)
220
#define EUSART0_CS_PA1 SILABS_DBUS_EUSART0_CS(0x0, 0x1)
221
#define EUSART0_CS_PA2 SILABS_DBUS_EUSART0_CS(0x0, 0x2)
222
#define EUSART0_CS_PA3 SILABS_DBUS_EUSART0_CS(0x0, 0x3)
223
#define EUSART0_CS_PA4 SILABS_DBUS_EUSART0_CS(0x0, 0x4)
224
#define EUSART0_CS_PA5 SILABS_DBUS_EUSART0_CS(0x0, 0x5)
225
#define EUSART0_CS_PA6 SILABS_DBUS_EUSART0_CS(0x0, 0x6)
226
#define EUSART0_CS_PA7 SILABS_DBUS_EUSART0_CS(0x0, 0x7)
227
#define EUSART0_CS_PA8 SILABS_DBUS_EUSART0_CS(0x0, 0x8)
228
#define EUSART0_CS_PB0 SILABS_DBUS_EUSART0_CS(0x1, 0x0)
229
#define EUSART0_CS_PB1 SILABS_DBUS_EUSART0_CS(0x1, 0x1)
230
#define EUSART0_CS_PB2 SILABS_DBUS_EUSART0_CS(0x1, 0x2)
231
#define EUSART0_CS_PB3 SILABS_DBUS_EUSART0_CS(0x1, 0x3)
232
#define EUSART0_CS_PB4 SILABS_DBUS_EUSART0_CS(0x1, 0x4)
233
#define EUSART0_CS_PC0 SILABS_DBUS_EUSART0_CS(0x2, 0x0)
234
#define EUSART0_CS_PC1 SILABS_DBUS_EUSART0_CS(0x2, 0x1)
235
#define EUSART0_CS_PC2 SILABS_DBUS_EUSART0_CS(0x2, 0x2)
236
#define EUSART0_CS_PC3 SILABS_DBUS_EUSART0_CS(0x2, 0x3)
237
#define EUSART0_CS_PC4 SILABS_DBUS_EUSART0_CS(0x2, 0x4)
238
#define EUSART0_CS_PC5 SILABS_DBUS_EUSART0_CS(0x2, 0x5)
239
#define EUSART0_CS_PC6 SILABS_DBUS_EUSART0_CS(0x2, 0x6)
240
#define EUSART0_CS_PC7 SILABS_DBUS_EUSART0_CS(0x2, 0x7)
241
#define EUSART0_CS_PD0 SILABS_DBUS_EUSART0_CS(0x3, 0x0)
242
#define EUSART0_CS_PD1 SILABS_DBUS_EUSART0_CS(0x3, 0x1)
243
#define EUSART0_CS_PD2 SILABS_DBUS_EUSART0_CS(0x3, 0x2)
244
#define EUSART0_CS_PD3 SILABS_DBUS_EUSART0_CS(0x3, 0x3)
245
#define EUSART0_RTS_PA0 SILABS_DBUS_EUSART0_RTS(0x0, 0x0)
246
#define EUSART0_RTS_PA1 SILABS_DBUS_EUSART0_RTS(0x0, 0x1)
247
#define EUSART0_RTS_PA2 SILABS_DBUS_EUSART0_RTS(0x0, 0x2)
248
#define EUSART0_RTS_PA3 SILABS_DBUS_EUSART0_RTS(0x0, 0x3)
249
#define EUSART0_RTS_PA4 SILABS_DBUS_EUSART0_RTS(0x0, 0x4)
250
#define EUSART0_RTS_PA5 SILABS_DBUS_EUSART0_RTS(0x0, 0x5)
251
#define EUSART0_RTS_PA6 SILABS_DBUS_EUSART0_RTS(0x0, 0x6)
252
#define EUSART0_RTS_PA7 SILABS_DBUS_EUSART0_RTS(0x0, 0x7)
253
#define EUSART0_RTS_PA8 SILABS_DBUS_EUSART0_RTS(0x0, 0x8)
254
#define EUSART0_RTS_PB0 SILABS_DBUS_EUSART0_RTS(0x1, 0x0)
255
#define EUSART0_RTS_PB1 SILABS_DBUS_EUSART0_RTS(0x1, 0x1)
256
#define EUSART0_RTS_PB2 SILABS_DBUS_EUSART0_RTS(0x1, 0x2)
257
#define EUSART0_RTS_PB3 SILABS_DBUS_EUSART0_RTS(0x1, 0x3)
258
#define EUSART0_RTS_PB4 SILABS_DBUS_EUSART0_RTS(0x1, 0x4)
259
#define EUSART0_RTS_PC0 SILABS_DBUS_EUSART0_RTS(0x2, 0x0)
260
#define EUSART0_RTS_PC1 SILABS_DBUS_EUSART0_RTS(0x2, 0x1)
261
#define EUSART0_RTS_PC2 SILABS_DBUS_EUSART0_RTS(0x2, 0x2)
262
#define EUSART0_RTS_PC3 SILABS_DBUS_EUSART0_RTS(0x2, 0x3)
263
#define EUSART0_RTS_PC4 SILABS_DBUS_EUSART0_RTS(0x2, 0x4)
264
#define EUSART0_RTS_PC5 SILABS_DBUS_EUSART0_RTS(0x2, 0x5)
265
#define EUSART0_RTS_PC6 SILABS_DBUS_EUSART0_RTS(0x2, 0x6)
266
#define EUSART0_RTS_PC7 SILABS_DBUS_EUSART0_RTS(0x2, 0x7)
267
#define EUSART0_RTS_PD0 SILABS_DBUS_EUSART0_RTS(0x3, 0x0)
268
#define EUSART0_RTS_PD1 SILABS_DBUS_EUSART0_RTS(0x3, 0x1)
269
#define EUSART0_RTS_PD2 SILABS_DBUS_EUSART0_RTS(0x3, 0x2)
270
#define EUSART0_RTS_PD3 SILABS_DBUS_EUSART0_RTS(0x3, 0x3)
271
#define EUSART0_RX_PA0 SILABS_DBUS_EUSART0_RX(0x0, 0x0)
272
#define EUSART0_RX_PA1 SILABS_DBUS_EUSART0_RX(0x0, 0x1)
273
#define EUSART0_RX_PA2 SILABS_DBUS_EUSART0_RX(0x0, 0x2)
274
#define EUSART0_RX_PA3 SILABS_DBUS_EUSART0_RX(0x0, 0x3)
275
#define EUSART0_RX_PA4 SILABS_DBUS_EUSART0_RX(0x0, 0x4)
276
#define EUSART0_RX_PA5 SILABS_DBUS_EUSART0_RX(0x0, 0x5)
277
#define EUSART0_RX_PA6 SILABS_DBUS_EUSART0_RX(0x0, 0x6)
278
#define EUSART0_RX_PA7 SILABS_DBUS_EUSART0_RX(0x0, 0x7)
279
#define EUSART0_RX_PA8 SILABS_DBUS_EUSART0_RX(0x0, 0x8)
280
#define EUSART0_RX_PB0 SILABS_DBUS_EUSART0_RX(0x1, 0x0)
281
#define EUSART0_RX_PB1 SILABS_DBUS_EUSART0_RX(0x1, 0x1)
282
#define EUSART0_RX_PB2 SILABS_DBUS_EUSART0_RX(0x1, 0x2)
283
#define EUSART0_RX_PB3 SILABS_DBUS_EUSART0_RX(0x1, 0x3)
284
#define EUSART0_RX_PB4 SILABS_DBUS_EUSART0_RX(0x1, 0x4)
285
#define EUSART0_RX_PC0 SILABS_DBUS_EUSART0_RX(0x2, 0x0)
286
#define EUSART0_RX_PC1 SILABS_DBUS_EUSART0_RX(0x2, 0x1)
287
#define EUSART0_RX_PC2 SILABS_DBUS_EUSART0_RX(0x2, 0x2)
288
#define EUSART0_RX_PC3 SILABS_DBUS_EUSART0_RX(0x2, 0x3)
289
#define EUSART0_RX_PC4 SILABS_DBUS_EUSART0_RX(0x2, 0x4)
290
#define EUSART0_RX_PC5 SILABS_DBUS_EUSART0_RX(0x2, 0x5)
291
#define EUSART0_RX_PC6 SILABS_DBUS_EUSART0_RX(0x2, 0x6)
292
#define EUSART0_RX_PC7 SILABS_DBUS_EUSART0_RX(0x2, 0x7)
293
#define EUSART0_RX_PD0 SILABS_DBUS_EUSART0_RX(0x3, 0x0)
294
#define EUSART0_RX_PD1 SILABS_DBUS_EUSART0_RX(0x3, 0x1)
295
#define EUSART0_RX_PD2 SILABS_DBUS_EUSART0_RX(0x3, 0x2)
296
#define EUSART0_RX_PD3 SILABS_DBUS_EUSART0_RX(0x3, 0x3)
297
#define EUSART0_SCLK_PA0 SILABS_DBUS_EUSART0_SCLK(0x0, 0x0)
298
#define EUSART0_SCLK_PA1 SILABS_DBUS_EUSART0_SCLK(0x0, 0x1)
299
#define EUSART0_SCLK_PA2 SILABS_DBUS_EUSART0_SCLK(0x0, 0x2)
300
#define EUSART0_SCLK_PA3 SILABS_DBUS_EUSART0_SCLK(0x0, 0x3)
301
#define EUSART0_SCLK_PA4 SILABS_DBUS_EUSART0_SCLK(0x0, 0x4)
302
#define EUSART0_SCLK_PA5 SILABS_DBUS_EUSART0_SCLK(0x0, 0x5)
303
#define EUSART0_SCLK_PA6 SILABS_DBUS_EUSART0_SCLK(0x0, 0x6)
304
#define EUSART0_SCLK_PA7 SILABS_DBUS_EUSART0_SCLK(0x0, 0x7)
305
#define EUSART0_SCLK_PA8 SILABS_DBUS_EUSART0_SCLK(0x0, 0x8)
306
#define EUSART0_SCLK_PB0 SILABS_DBUS_EUSART0_SCLK(0x1, 0x0)
307
#define EUSART0_SCLK_PB1 SILABS_DBUS_EUSART0_SCLK(0x1, 0x1)
308
#define EUSART0_SCLK_PB2 SILABS_DBUS_EUSART0_SCLK(0x1, 0x2)
309
#define EUSART0_SCLK_PB3 SILABS_DBUS_EUSART0_SCLK(0x1, 0x3)
310
#define EUSART0_SCLK_PB4 SILABS_DBUS_EUSART0_SCLK(0x1, 0x4)
311
#define EUSART0_SCLK_PC0 SILABS_DBUS_EUSART0_SCLK(0x2, 0x0)
312
#define EUSART0_SCLK_PC1 SILABS_DBUS_EUSART0_SCLK(0x2, 0x1)
313
#define EUSART0_SCLK_PC2 SILABS_DBUS_EUSART0_SCLK(0x2, 0x2)
314
#define EUSART0_SCLK_PC3 SILABS_DBUS_EUSART0_SCLK(0x2, 0x3)
315
#define EUSART0_SCLK_PC4 SILABS_DBUS_EUSART0_SCLK(0x2, 0x4)
316
#define EUSART0_SCLK_PC5 SILABS_DBUS_EUSART0_SCLK(0x2, 0x5)
317
#define EUSART0_SCLK_PC6 SILABS_DBUS_EUSART0_SCLK(0x2, 0x6)
318
#define EUSART0_SCLK_PC7 SILABS_DBUS_EUSART0_SCLK(0x2, 0x7)
319
#define EUSART0_SCLK_PD0 SILABS_DBUS_EUSART0_SCLK(0x3, 0x0)
320
#define EUSART0_SCLK_PD1 SILABS_DBUS_EUSART0_SCLK(0x3, 0x1)
321
#define EUSART0_SCLK_PD2 SILABS_DBUS_EUSART0_SCLK(0x3, 0x2)
322
#define EUSART0_SCLK_PD3 SILABS_DBUS_EUSART0_SCLK(0x3, 0x3)
323
#define EUSART0_TX_PA0 SILABS_DBUS_EUSART0_TX(0x0, 0x0)
324
#define EUSART0_TX_PA1 SILABS_DBUS_EUSART0_TX(0x0, 0x1)
325
#define EUSART0_TX_PA2 SILABS_DBUS_EUSART0_TX(0x0, 0x2)
326
#define EUSART0_TX_PA3 SILABS_DBUS_EUSART0_TX(0x0, 0x3)
327
#define EUSART0_TX_PA4 SILABS_DBUS_EUSART0_TX(0x0, 0x4)
328
#define EUSART0_TX_PA5 SILABS_DBUS_EUSART0_TX(0x0, 0x5)
329
#define EUSART0_TX_PA6 SILABS_DBUS_EUSART0_TX(0x0, 0x6)
330
#define EUSART0_TX_PA7 SILABS_DBUS_EUSART0_TX(0x0, 0x7)
331
#define EUSART0_TX_PA8 SILABS_DBUS_EUSART0_TX(0x0, 0x8)
332
#define EUSART0_TX_PB0 SILABS_DBUS_EUSART0_TX(0x1, 0x0)
333
#define EUSART0_TX_PB1 SILABS_DBUS_EUSART0_TX(0x1, 0x1)
334
#define EUSART0_TX_PB2 SILABS_DBUS_EUSART0_TX(0x1, 0x2)
335
#define EUSART0_TX_PB3 SILABS_DBUS_EUSART0_TX(0x1, 0x3)
336
#define EUSART0_TX_PB4 SILABS_DBUS_EUSART0_TX(0x1, 0x4)
337
#define EUSART0_TX_PC0 SILABS_DBUS_EUSART0_TX(0x2, 0x0)
338
#define EUSART0_TX_PC1 SILABS_DBUS_EUSART0_TX(0x2, 0x1)
339
#define EUSART0_TX_PC2 SILABS_DBUS_EUSART0_TX(0x2, 0x2)
340
#define EUSART0_TX_PC3 SILABS_DBUS_EUSART0_TX(0x2, 0x3)
341
#define EUSART0_TX_PC4 SILABS_DBUS_EUSART0_TX(0x2, 0x4)
342
#define EUSART0_TX_PC5 SILABS_DBUS_EUSART0_TX(0x2, 0x5)
343
#define EUSART0_TX_PC6 SILABS_DBUS_EUSART0_TX(0x2, 0x6)
344
#define EUSART0_TX_PC7 SILABS_DBUS_EUSART0_TX(0x2, 0x7)
345
#define EUSART0_TX_PD0 SILABS_DBUS_EUSART0_TX(0x3, 0x0)
346
#define EUSART0_TX_PD1 SILABS_DBUS_EUSART0_TX(0x3, 0x1)
347
#define EUSART0_TX_PD2 SILABS_DBUS_EUSART0_TX(0x3, 0x2)
348
#define EUSART0_TX_PD3 SILABS_DBUS_EUSART0_TX(0x3, 0x3)
349
#define EUSART0_CTS_PA0 SILABS_DBUS_EUSART0_CTS(0x0, 0x0)
350
#define EUSART0_CTS_PA1 SILABS_DBUS_EUSART0_CTS(0x0, 0x1)
351
#define EUSART0_CTS_PA2 SILABS_DBUS_EUSART0_CTS(0x0, 0x2)
352
#define EUSART0_CTS_PA3 SILABS_DBUS_EUSART0_CTS(0x0, 0x3)
353
#define EUSART0_CTS_PA4 SILABS_DBUS_EUSART0_CTS(0x0, 0x4)
354
#define EUSART0_CTS_PA5 SILABS_DBUS_EUSART0_CTS(0x0, 0x5)
355
#define EUSART0_CTS_PA6 SILABS_DBUS_EUSART0_CTS(0x0, 0x6)
356
#define EUSART0_CTS_PA7 SILABS_DBUS_EUSART0_CTS(0x0, 0x7)
357
#define EUSART0_CTS_PA8 SILABS_DBUS_EUSART0_CTS(0x0, 0x8)
358
#define EUSART0_CTS_PB0 SILABS_DBUS_EUSART0_CTS(0x1, 0x0)
359
#define EUSART0_CTS_PB1 SILABS_DBUS_EUSART0_CTS(0x1, 0x1)
360
#define EUSART0_CTS_PB2 SILABS_DBUS_EUSART0_CTS(0x1, 0x2)
361
#define EUSART0_CTS_PB3 SILABS_DBUS_EUSART0_CTS(0x1, 0x3)
362
#define EUSART0_CTS_PB4 SILABS_DBUS_EUSART0_CTS(0x1, 0x4)
363
#define EUSART0_CTS_PC0 SILABS_DBUS_EUSART0_CTS(0x2, 0x0)
364
#define EUSART0_CTS_PC1 SILABS_DBUS_EUSART0_CTS(0x2, 0x1)
365
#define EUSART0_CTS_PC2 SILABS_DBUS_EUSART0_CTS(0x2, 0x2)
366
#define EUSART0_CTS_PC3 SILABS_DBUS_EUSART0_CTS(0x2, 0x3)
367
#define EUSART0_CTS_PC4 SILABS_DBUS_EUSART0_CTS(0x2, 0x4)
368
#define EUSART0_CTS_PC5 SILABS_DBUS_EUSART0_CTS(0x2, 0x5)
369
#define EUSART0_CTS_PC6 SILABS_DBUS_EUSART0_CTS(0x2, 0x6)
370
#define EUSART0_CTS_PC7 SILABS_DBUS_EUSART0_CTS(0x2, 0x7)
371
#define EUSART0_CTS_PD0 SILABS_DBUS_EUSART0_CTS(0x3, 0x0)
372
#define EUSART0_CTS_PD1 SILABS_DBUS_EUSART0_CTS(0x3, 0x1)
373
#define EUSART0_CTS_PD2 SILABS_DBUS_EUSART0_CTS(0x3, 0x2)
374
#define EUSART0_CTS_PD3 SILABS_DBUS_EUSART0_CTS(0x3, 0x3)
375
376
#define PTI_DCLK_PC0 SILABS_DBUS_PTI_DCLK(0x2, 0x0)
377
#define PTI_DCLK_PC1 SILABS_DBUS_PTI_DCLK(0x2, 0x1)
378
#define PTI_DCLK_PC2 SILABS_DBUS_PTI_DCLK(0x2, 0x2)
379
#define PTI_DCLK_PC3 SILABS_DBUS_PTI_DCLK(0x2, 0x3)
380
#define PTI_DCLK_PC4 SILABS_DBUS_PTI_DCLK(0x2, 0x4)
381
#define PTI_DCLK_PC5 SILABS_DBUS_PTI_DCLK(0x2, 0x5)
382
#define PTI_DCLK_PC6 SILABS_DBUS_PTI_DCLK(0x2, 0x6)
383
#define PTI_DCLK_PC7 SILABS_DBUS_PTI_DCLK(0x2, 0x7)
384
#define PTI_DCLK_PD0 SILABS_DBUS_PTI_DCLK(0x3, 0x0)
385
#define PTI_DCLK_PD1 SILABS_DBUS_PTI_DCLK(0x3, 0x1)
386
#define PTI_DCLK_PD2 SILABS_DBUS_PTI_DCLK(0x3, 0x2)
387
#define PTI_DCLK_PD3 SILABS_DBUS_PTI_DCLK(0x3, 0x3)
388
#define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0)
389
#define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1)
390
#define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2)
391
#define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3)
392
#define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4)
393
#define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5)
394
#define PTI_DFRAME_PC6 SILABS_DBUS_PTI_DFRAME(0x2, 0x6)
395
#define PTI_DFRAME_PC7 SILABS_DBUS_PTI_DFRAME(0x2, 0x7)
396
#define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0)
397
#define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1)
398
#define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2)
399
#define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3)
400
#define PTI_DOUT_PC0 SILABS_DBUS_PTI_DOUT(0x2, 0x0)
401
#define PTI_DOUT_PC1 SILABS_DBUS_PTI_DOUT(0x2, 0x1)
402
#define PTI_DOUT_PC2 SILABS_DBUS_PTI_DOUT(0x2, 0x2)
403
#define PTI_DOUT_PC3 SILABS_DBUS_PTI_DOUT(0x2, 0x3)
404
#define PTI_DOUT_PC4 SILABS_DBUS_PTI_DOUT(0x2, 0x4)
405
#define PTI_DOUT_PC5 SILABS_DBUS_PTI_DOUT(0x2, 0x5)
406
#define PTI_DOUT_PC6 SILABS_DBUS_PTI_DOUT(0x2, 0x6)
407
#define PTI_DOUT_PC7 SILABS_DBUS_PTI_DOUT(0x2, 0x7)
408
#define PTI_DOUT_PD0 SILABS_DBUS_PTI_DOUT(0x3, 0x0)
409
#define PTI_DOUT_PD1 SILABS_DBUS_PTI_DOUT(0x3, 0x1)
410
#define PTI_DOUT_PD2 SILABS_DBUS_PTI_DOUT(0x3, 0x2)
411
#define PTI_DOUT_PD3 SILABS_DBUS_PTI_DOUT(0x3, 0x3)
412
413
#define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0)
414
#define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1)
415
#define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2)
416
#define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3)
417
#define I2C0_SCL_PA4 SILABS_DBUS_I2C0_SCL(0x0, 0x4)
418
#define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5)
419
#define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6)
420
#define I2C0_SCL_PA7 SILABS_DBUS_I2C0_SCL(0x0, 0x7)
421
#define I2C0_SCL_PA8 SILABS_DBUS_I2C0_SCL(0x0, 0x8)
422
#define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0)
423
#define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1)
424
#define I2C0_SCL_PB2 SILABS_DBUS_I2C0_SCL(0x1, 0x2)
425
#define I2C0_SCL_PB3 SILABS_DBUS_I2C0_SCL(0x1, 0x3)
426
#define I2C0_SCL_PB4 SILABS_DBUS_I2C0_SCL(0x1, 0x4)
427
#define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0)
428
#define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1)
429
#define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2)
430
#define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3)
431
#define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4)
432
#define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5)
433
#define I2C0_SCL_PC6 SILABS_DBUS_I2C0_SCL(0x2, 0x6)
434
#define I2C0_SCL_PC7 SILABS_DBUS_I2C0_SCL(0x2, 0x7)
435
#define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0)
436
#define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1)
437
#define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2)
438
#define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3)
439
#define I2C0_SDA_PA0 SILABS_DBUS_I2C0_SDA(0x0, 0x0)
440
#define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1)
441
#define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2)
442
#define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3)
443
#define I2C0_SDA_PA4 SILABS_DBUS_I2C0_SDA(0x0, 0x4)
444
#define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5)
445
#define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6)
446
#define I2C0_SDA_PA7 SILABS_DBUS_I2C0_SDA(0x0, 0x7)
447
#define I2C0_SDA_PA8 SILABS_DBUS_I2C0_SDA(0x0, 0x8)
448
#define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0)
449
#define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1)
450
#define I2C0_SDA_PB2 SILABS_DBUS_I2C0_SDA(0x1, 0x2)
451
#define I2C0_SDA_PB3 SILABS_DBUS_I2C0_SDA(0x1, 0x3)
452
#define I2C0_SDA_PB4 SILABS_DBUS_I2C0_SDA(0x1, 0x4)
453
#define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0)
454
#define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1)
455
#define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2)
456
#define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3)
457
#define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4)
458
#define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5)
459
#define I2C0_SDA_PC6 SILABS_DBUS_I2C0_SDA(0x2, 0x6)
460
#define I2C0_SDA_PC7 SILABS_DBUS_I2C0_SDA(0x2, 0x7)
461
#define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0)
462
#define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1)
463
#define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2)
464
#define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3)
465
466
#define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0)
467
#define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1)
468
#define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2)
469
#define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3)
470
#define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4)
471
#define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5)
472
#define I2C1_SCL_PC6 SILABS_DBUS_I2C1_SCL(0x2, 0x6)
473
#define I2C1_SCL_PC7 SILABS_DBUS_I2C1_SCL(0x2, 0x7)
474
#define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0)
475
#define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1)
476
#define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2)
477
#define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3)
478
#define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0)
479
#define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1)
480
#define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2)
481
#define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3)
482
#define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4)
483
#define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5)
484
#define I2C1_SDA_PC6 SILABS_DBUS_I2C1_SDA(0x2, 0x6)
485
#define I2C1_SDA_PC7 SILABS_DBUS_I2C1_SDA(0x2, 0x7)
486
#define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0)
487
#define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1)
488
#define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2)
489
#define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3)
490
491
#define LETIMER0_OUT0_PA0 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x0)
492
#define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1)
493
#define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2)
494
#define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3)
495
#define LETIMER0_OUT0_PA4 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x4)
496
#define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5)
497
#define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6)
498
#define LETIMER0_OUT0_PA7 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x7)
499
#define LETIMER0_OUT0_PA8 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x8)
500
#define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0)
501
#define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1)
502
#define LETIMER0_OUT0_PB2 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x2)
503
#define LETIMER0_OUT0_PB3 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x3)
504
#define LETIMER0_OUT0_PB4 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x4)
505
#define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x0)
506
#define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1)
507
#define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2)
508
#define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3)
509
#define LETIMER0_OUT1_PA4 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x4)
510
#define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5)
511
#define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6)
512
#define LETIMER0_OUT1_PA7 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x7)
513
#define LETIMER0_OUT1_PA8 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x8)
514
#define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0)
515
#define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1)
516
#define LETIMER0_OUT1_PB2 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x2)
517
#define LETIMER0_OUT1_PB3 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x3)
518
#define LETIMER0_OUT1_PB4 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x4)
519
520
#define MODEM_ANT0_PA0 SILABS_DBUS_MODEM_ANT0(0x0, 0x0)
521
#define MODEM_ANT0_PA1 SILABS_DBUS_MODEM_ANT0(0x0, 0x1)
522
#define MODEM_ANT0_PA2 SILABS_DBUS_MODEM_ANT0(0x0, 0x2)
523
#define MODEM_ANT0_PA3 SILABS_DBUS_MODEM_ANT0(0x0, 0x3)
524
#define MODEM_ANT0_PA4 SILABS_DBUS_MODEM_ANT0(0x0, 0x4)
525
#define MODEM_ANT0_PA5 SILABS_DBUS_MODEM_ANT0(0x0, 0x5)
526
#define MODEM_ANT0_PA6 SILABS_DBUS_MODEM_ANT0(0x0, 0x6)
527
#define MODEM_ANT0_PA7 SILABS_DBUS_MODEM_ANT0(0x0, 0x7)
528
#define MODEM_ANT0_PA8 SILABS_DBUS_MODEM_ANT0(0x0, 0x8)
529
#define MODEM_ANT0_PB0 SILABS_DBUS_MODEM_ANT0(0x1, 0x0)
530
#define MODEM_ANT0_PB1 SILABS_DBUS_MODEM_ANT0(0x1, 0x1)
531
#define MODEM_ANT0_PB2 SILABS_DBUS_MODEM_ANT0(0x1, 0x2)
532
#define MODEM_ANT0_PB3 SILABS_DBUS_MODEM_ANT0(0x1, 0x3)
533
#define MODEM_ANT0_PB4 SILABS_DBUS_MODEM_ANT0(0x1, 0x4)
534
#define MODEM_ANT0_PC0 SILABS_DBUS_MODEM_ANT0(0x2, 0x0)
535
#define MODEM_ANT0_PC1 SILABS_DBUS_MODEM_ANT0(0x2, 0x1)
536
#define MODEM_ANT0_PC2 SILABS_DBUS_MODEM_ANT0(0x2, 0x2)
537
#define MODEM_ANT0_PC3 SILABS_DBUS_MODEM_ANT0(0x2, 0x3)
538
#define MODEM_ANT0_PC4 SILABS_DBUS_MODEM_ANT0(0x2, 0x4)
539
#define MODEM_ANT0_PC5 SILABS_DBUS_MODEM_ANT0(0x2, 0x5)
540
#define MODEM_ANT0_PC6 SILABS_DBUS_MODEM_ANT0(0x2, 0x6)
541
#define MODEM_ANT0_PC7 SILABS_DBUS_MODEM_ANT0(0x2, 0x7)
542
#define MODEM_ANT0_PD0 SILABS_DBUS_MODEM_ANT0(0x3, 0x0)
543
#define MODEM_ANT0_PD1 SILABS_DBUS_MODEM_ANT0(0x3, 0x1)
544
#define MODEM_ANT0_PD2 SILABS_DBUS_MODEM_ANT0(0x3, 0x2)
545
#define MODEM_ANT0_PD3 SILABS_DBUS_MODEM_ANT0(0x3, 0x3)
546
#define MODEM_ANT1_PA0 SILABS_DBUS_MODEM_ANT1(0x0, 0x0)
547
#define MODEM_ANT1_PA1 SILABS_DBUS_MODEM_ANT1(0x0, 0x1)
548
#define MODEM_ANT1_PA2 SILABS_DBUS_MODEM_ANT1(0x0, 0x2)
549
#define MODEM_ANT1_PA3 SILABS_DBUS_MODEM_ANT1(0x0, 0x3)
550
#define MODEM_ANT1_PA4 SILABS_DBUS_MODEM_ANT1(0x0, 0x4)
551
#define MODEM_ANT1_PA5 SILABS_DBUS_MODEM_ANT1(0x0, 0x5)
552
#define MODEM_ANT1_PA6 SILABS_DBUS_MODEM_ANT1(0x0, 0x6)
553
#define MODEM_ANT1_PA7 SILABS_DBUS_MODEM_ANT1(0x0, 0x7)
554
#define MODEM_ANT1_PA8 SILABS_DBUS_MODEM_ANT1(0x0, 0x8)
555
#define MODEM_ANT1_PB0 SILABS_DBUS_MODEM_ANT1(0x1, 0x0)
556
#define MODEM_ANT1_PB1 SILABS_DBUS_MODEM_ANT1(0x1, 0x1)
557
#define MODEM_ANT1_PB2 SILABS_DBUS_MODEM_ANT1(0x1, 0x2)
558
#define MODEM_ANT1_PB3 SILABS_DBUS_MODEM_ANT1(0x1, 0x3)
559
#define MODEM_ANT1_PB4 SILABS_DBUS_MODEM_ANT1(0x1, 0x4)
560
#define MODEM_ANT1_PC0 SILABS_DBUS_MODEM_ANT1(0x2, 0x0)
561
#define MODEM_ANT1_PC1 SILABS_DBUS_MODEM_ANT1(0x2, 0x1)
562
#define MODEM_ANT1_PC2 SILABS_DBUS_MODEM_ANT1(0x2, 0x2)
563
#define MODEM_ANT1_PC3 SILABS_DBUS_MODEM_ANT1(0x2, 0x3)
564
#define MODEM_ANT1_PC4 SILABS_DBUS_MODEM_ANT1(0x2, 0x4)
565
#define MODEM_ANT1_PC5 SILABS_DBUS_MODEM_ANT1(0x2, 0x5)
566
#define MODEM_ANT1_PC6 SILABS_DBUS_MODEM_ANT1(0x2, 0x6)
567
#define MODEM_ANT1_PC7 SILABS_DBUS_MODEM_ANT1(0x2, 0x7)
568
#define MODEM_ANT1_PD0 SILABS_DBUS_MODEM_ANT1(0x3, 0x0)
569
#define MODEM_ANT1_PD1 SILABS_DBUS_MODEM_ANT1(0x3, 0x1)
570
#define MODEM_ANT1_PD2 SILABS_DBUS_MODEM_ANT1(0x3, 0x2)
571
#define MODEM_ANT1_PD3 SILABS_DBUS_MODEM_ANT1(0x3, 0x3)
572
#define MODEM_ANTROLLOVER_PC0 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x0)
573
#define MODEM_ANTROLLOVER_PC1 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x1)
574
#define MODEM_ANTROLLOVER_PC2 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x2)
575
#define MODEM_ANTROLLOVER_PC3 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x3)
576
#define MODEM_ANTROLLOVER_PC4 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x4)
577
#define MODEM_ANTROLLOVER_PC5 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x5)
578
#define MODEM_ANTROLLOVER_PC6 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x6)
579
#define MODEM_ANTROLLOVER_PC7 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x7)
580
#define MODEM_ANTROLLOVER_PD0 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x0)
581
#define MODEM_ANTROLLOVER_PD1 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x1)
582
#define MODEM_ANTROLLOVER_PD2 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x2)
583
#define MODEM_ANTROLLOVER_PD3 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x3)
584
#define MODEM_ANTRR0_PC0 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x0)
585
#define MODEM_ANTRR0_PC1 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x1)
586
#define MODEM_ANTRR0_PC2 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x2)
587
#define MODEM_ANTRR0_PC3 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x3)
588
#define MODEM_ANTRR0_PC4 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x4)
589
#define MODEM_ANTRR0_PC5 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x5)
590
#define MODEM_ANTRR0_PC6 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x6)
591
#define MODEM_ANTRR0_PC7 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x7)
592
#define MODEM_ANTRR0_PD0 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x0)
593
#define MODEM_ANTRR0_PD1 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x1)
594
#define MODEM_ANTRR0_PD2 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x2)
595
#define MODEM_ANTRR0_PD3 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x3)
596
#define MODEM_ANTRR1_PC0 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x0)
597
#define MODEM_ANTRR1_PC1 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x1)
598
#define MODEM_ANTRR1_PC2 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x2)
599
#define MODEM_ANTRR1_PC3 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x3)
600
#define MODEM_ANTRR1_PC4 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x4)
601
#define MODEM_ANTRR1_PC5 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x5)
602
#define MODEM_ANTRR1_PC6 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x6)
603
#define MODEM_ANTRR1_PC7 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x7)
604
#define MODEM_ANTRR1_PD0 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x0)
605
#define MODEM_ANTRR1_PD1 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x1)
606
#define MODEM_ANTRR1_PD2 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x2)
607
#define MODEM_ANTRR1_PD3 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x3)
608
#define MODEM_ANTRR2_PC0 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x0)
609
#define MODEM_ANTRR2_PC1 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x1)
610
#define MODEM_ANTRR2_PC2 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x2)
611
#define MODEM_ANTRR2_PC3 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x3)
612
#define MODEM_ANTRR2_PC4 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x4)
613
#define MODEM_ANTRR2_PC5 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x5)
614
#define MODEM_ANTRR2_PC6 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x6)
615
#define MODEM_ANTRR2_PC7 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x7)
616
#define MODEM_ANTRR2_PD0 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x0)
617
#define MODEM_ANTRR2_PD1 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x1)
618
#define MODEM_ANTRR2_PD2 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x2)
619
#define MODEM_ANTRR2_PD3 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x3)
620
#define MODEM_ANTRR3_PC0 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x0)
621
#define MODEM_ANTRR3_PC1 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x1)
622
#define MODEM_ANTRR3_PC2 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x2)
623
#define MODEM_ANTRR3_PC3 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x3)
624
#define MODEM_ANTRR3_PC4 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x4)
625
#define MODEM_ANTRR3_PC5 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x5)
626
#define MODEM_ANTRR3_PC6 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x6)
627
#define MODEM_ANTRR3_PC7 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x7)
628
#define MODEM_ANTRR3_PD0 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x0)
629
#define MODEM_ANTRR3_PD1 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x1)
630
#define MODEM_ANTRR3_PD2 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x2)
631
#define MODEM_ANTRR3_PD3 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x3)
632
#define MODEM_ANTRR4_PC0 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x0)
633
#define MODEM_ANTRR4_PC1 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x1)
634
#define MODEM_ANTRR4_PC2 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x2)
635
#define MODEM_ANTRR4_PC3 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x3)
636
#define MODEM_ANTRR4_PC4 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x4)
637
#define MODEM_ANTRR4_PC5 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x5)
638
#define MODEM_ANTRR4_PC6 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x6)
639
#define MODEM_ANTRR4_PC7 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x7)
640
#define MODEM_ANTRR4_PD0 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x0)
641
#define MODEM_ANTRR4_PD1 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x1)
642
#define MODEM_ANTRR4_PD2 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x2)
643
#define MODEM_ANTRR4_PD3 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x3)
644
#define MODEM_ANTRR5_PC0 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x0)
645
#define MODEM_ANTRR5_PC1 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x1)
646
#define MODEM_ANTRR5_PC2 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x2)
647
#define MODEM_ANTRR5_PC3 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x3)
648
#define MODEM_ANTRR5_PC4 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x4)
649
#define MODEM_ANTRR5_PC5 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x5)
650
#define MODEM_ANTRR5_PC6 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x6)
651
#define MODEM_ANTRR5_PC7 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x7)
652
#define MODEM_ANTRR5_PD0 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x0)
653
#define MODEM_ANTRR5_PD1 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x1)
654
#define MODEM_ANTRR5_PD2 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x2)
655
#define MODEM_ANTRR5_PD3 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x3)
656
#define MODEM_ANTSWEN_PC0 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x0)
657
#define MODEM_ANTSWEN_PC1 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x1)
658
#define MODEM_ANTSWEN_PC2 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x2)
659
#define MODEM_ANTSWEN_PC3 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x3)
660
#define MODEM_ANTSWEN_PC4 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x4)
661
#define MODEM_ANTSWEN_PC5 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x5)
662
#define MODEM_ANTSWEN_PC6 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x6)
663
#define MODEM_ANTSWEN_PC7 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x7)
664
#define MODEM_ANTSWEN_PD0 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x0)
665
#define MODEM_ANTSWEN_PD1 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x1)
666
#define MODEM_ANTSWEN_PD2 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x2)
667
#define MODEM_ANTSWEN_PD3 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x3)
668
#define MODEM_ANTSWUS_PC0 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x0)
669
#define MODEM_ANTSWUS_PC1 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x1)
670
#define MODEM_ANTSWUS_PC2 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x2)
671
#define MODEM_ANTSWUS_PC3 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x3)
672
#define MODEM_ANTSWUS_PC4 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x4)
673
#define MODEM_ANTSWUS_PC5 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x5)
674
#define MODEM_ANTSWUS_PC6 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x6)
675
#define MODEM_ANTSWUS_PC7 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x7)
676
#define MODEM_ANTSWUS_PD0 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x0)
677
#define MODEM_ANTSWUS_PD1 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x1)
678
#define MODEM_ANTSWUS_PD2 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x2)
679
#define MODEM_ANTSWUS_PD3 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x3)
680
#define MODEM_ANTTRIG_PC0 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x0)
681
#define MODEM_ANTTRIG_PC1 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x1)
682
#define MODEM_ANTTRIG_PC2 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x2)
683
#define MODEM_ANTTRIG_PC3 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x3)
684
#define MODEM_ANTTRIG_PC4 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x4)
685
#define MODEM_ANTTRIG_PC5 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x5)
686
#define MODEM_ANTTRIG_PC6 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x6)
687
#define MODEM_ANTTRIG_PC7 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x7)
688
#define MODEM_ANTTRIG_PD0 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x0)
689
#define MODEM_ANTTRIG_PD1 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x1)
690
#define MODEM_ANTTRIG_PD2 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x2)
691
#define MODEM_ANTTRIG_PD3 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x3)
692
#define MODEM_ANTTRIGSTOP_PC0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x0)
693
#define MODEM_ANTTRIGSTOP_PC1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x1)
694
#define MODEM_ANTTRIGSTOP_PC2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x2)
695
#define MODEM_ANTTRIGSTOP_PC3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x3)
696
#define MODEM_ANTTRIGSTOP_PC4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x4)
697
#define MODEM_ANTTRIGSTOP_PC5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x5)
698
#define MODEM_ANTTRIGSTOP_PC6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x6)
699
#define MODEM_ANTTRIGSTOP_PC7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x7)
700
#define MODEM_ANTTRIGSTOP_PD0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x0)
701
#define MODEM_ANTTRIGSTOP_PD1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x1)
702
#define MODEM_ANTTRIGSTOP_PD2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x2)
703
#define MODEM_ANTTRIGSTOP_PD3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x3)
704
#define MODEM_DCLK_PA0 SILABS_DBUS_MODEM_DCLK(0x0, 0x0)
705
#define MODEM_DCLK_PA1 SILABS_DBUS_MODEM_DCLK(0x0, 0x1)
706
#define MODEM_DCLK_PA2 SILABS_DBUS_MODEM_DCLK(0x0, 0x2)
707
#define MODEM_DCLK_PA3 SILABS_DBUS_MODEM_DCLK(0x0, 0x3)
708
#define MODEM_DCLK_PA4 SILABS_DBUS_MODEM_DCLK(0x0, 0x4)
709
#define MODEM_DCLK_PA5 SILABS_DBUS_MODEM_DCLK(0x0, 0x5)
710
#define MODEM_DCLK_PA6 SILABS_DBUS_MODEM_DCLK(0x0, 0x6)
711
#define MODEM_DCLK_PA7 SILABS_DBUS_MODEM_DCLK(0x0, 0x7)
712
#define MODEM_DCLK_PA8 SILABS_DBUS_MODEM_DCLK(0x0, 0x8)
713
#define MODEM_DCLK_PB0 SILABS_DBUS_MODEM_DCLK(0x1, 0x0)
714
#define MODEM_DCLK_PB1 SILABS_DBUS_MODEM_DCLK(0x1, 0x1)
715
#define MODEM_DCLK_PB2 SILABS_DBUS_MODEM_DCLK(0x1, 0x2)
716
#define MODEM_DCLK_PB3 SILABS_DBUS_MODEM_DCLK(0x1, 0x3)
717
#define MODEM_DCLK_PB4 SILABS_DBUS_MODEM_DCLK(0x1, 0x4)
718
#define MODEM_DOUT_PA0 SILABS_DBUS_MODEM_DOUT(0x0, 0x0)
719
#define MODEM_DOUT_PA1 SILABS_DBUS_MODEM_DOUT(0x0, 0x1)
720
#define MODEM_DOUT_PA2 SILABS_DBUS_MODEM_DOUT(0x0, 0x2)
721
#define MODEM_DOUT_PA3 SILABS_DBUS_MODEM_DOUT(0x0, 0x3)
722
#define MODEM_DOUT_PA4 SILABS_DBUS_MODEM_DOUT(0x0, 0x4)
723
#define MODEM_DOUT_PA5 SILABS_DBUS_MODEM_DOUT(0x0, 0x5)
724
#define MODEM_DOUT_PA6 SILABS_DBUS_MODEM_DOUT(0x0, 0x6)
725
#define MODEM_DOUT_PA7 SILABS_DBUS_MODEM_DOUT(0x0, 0x7)
726
#define MODEM_DOUT_PA8 SILABS_DBUS_MODEM_DOUT(0x0, 0x8)
727
#define MODEM_DOUT_PB0 SILABS_DBUS_MODEM_DOUT(0x1, 0x0)
728
#define MODEM_DOUT_PB1 SILABS_DBUS_MODEM_DOUT(0x1, 0x1)
729
#define MODEM_DOUT_PB2 SILABS_DBUS_MODEM_DOUT(0x1, 0x2)
730
#define MODEM_DOUT_PB3 SILABS_DBUS_MODEM_DOUT(0x1, 0x3)
731
#define MODEM_DOUT_PB4 SILABS_DBUS_MODEM_DOUT(0x1, 0x4)
732
#define MODEM_DIN_PA0 SILABS_DBUS_MODEM_DIN(0x0, 0x0)
733
#define MODEM_DIN_PA1 SILABS_DBUS_MODEM_DIN(0x0, 0x1)
734
#define MODEM_DIN_PA2 SILABS_DBUS_MODEM_DIN(0x0, 0x2)
735
#define MODEM_DIN_PA3 SILABS_DBUS_MODEM_DIN(0x0, 0x3)
736
#define MODEM_DIN_PA4 SILABS_DBUS_MODEM_DIN(0x0, 0x4)
737
#define MODEM_DIN_PA5 SILABS_DBUS_MODEM_DIN(0x0, 0x5)
738
#define MODEM_DIN_PA6 SILABS_DBUS_MODEM_DIN(0x0, 0x6)
739
#define MODEM_DIN_PA7 SILABS_DBUS_MODEM_DIN(0x0, 0x7)
740
#define MODEM_DIN_PA8 SILABS_DBUS_MODEM_DIN(0x0, 0x8)
741
#define MODEM_DIN_PB0 SILABS_DBUS_MODEM_DIN(0x1, 0x0)
742
#define MODEM_DIN_PB1 SILABS_DBUS_MODEM_DIN(0x1, 0x1)
743
#define MODEM_DIN_PB2 SILABS_DBUS_MODEM_DIN(0x1, 0x2)
744
#define MODEM_DIN_PB3 SILABS_DBUS_MODEM_DIN(0x1, 0x3)
745
#define MODEM_DIN_PB4 SILABS_DBUS_MODEM_DIN(0x1, 0x4)
746
747
#define PDM_CLK_PA0 SILABS_DBUS_PDM_CLK(0x0, 0x0)
748
#define PDM_CLK_PA1 SILABS_DBUS_PDM_CLK(0x0, 0x1)
749
#define PDM_CLK_PA2 SILABS_DBUS_PDM_CLK(0x0, 0x2)
750
#define PDM_CLK_PA3 SILABS_DBUS_PDM_CLK(0x0, 0x3)
751
#define PDM_CLK_PA4 SILABS_DBUS_PDM_CLK(0x0, 0x4)
752
#define PDM_CLK_PA5 SILABS_DBUS_PDM_CLK(0x0, 0x5)
753
#define PDM_CLK_PA6 SILABS_DBUS_PDM_CLK(0x0, 0x6)
754
#define PDM_CLK_PA7 SILABS_DBUS_PDM_CLK(0x0, 0x7)
755
#define PDM_CLK_PA8 SILABS_DBUS_PDM_CLK(0x0, 0x8)
756
#define PDM_CLK_PB0 SILABS_DBUS_PDM_CLK(0x1, 0x0)
757
#define PDM_CLK_PB1 SILABS_DBUS_PDM_CLK(0x1, 0x1)
758
#define PDM_CLK_PB2 SILABS_DBUS_PDM_CLK(0x1, 0x2)
759
#define PDM_CLK_PB3 SILABS_DBUS_PDM_CLK(0x1, 0x3)
760
#define PDM_CLK_PB4 SILABS_DBUS_PDM_CLK(0x1, 0x4)
761
#define PDM_CLK_PC0 SILABS_DBUS_PDM_CLK(0x2, 0x0)
762
#define PDM_CLK_PC1 SILABS_DBUS_PDM_CLK(0x2, 0x1)
763
#define PDM_CLK_PC2 SILABS_DBUS_PDM_CLK(0x2, 0x2)
764
#define PDM_CLK_PC3 SILABS_DBUS_PDM_CLK(0x2, 0x3)
765
#define PDM_CLK_PC4 SILABS_DBUS_PDM_CLK(0x2, 0x4)
766
#define PDM_CLK_PC5 SILABS_DBUS_PDM_CLK(0x2, 0x5)
767
#define PDM_CLK_PC6 SILABS_DBUS_PDM_CLK(0x2, 0x6)
768
#define PDM_CLK_PC7 SILABS_DBUS_PDM_CLK(0x2, 0x7)
769
#define PDM_CLK_PD0 SILABS_DBUS_PDM_CLK(0x3, 0x0)
770
#define PDM_CLK_PD1 SILABS_DBUS_PDM_CLK(0x3, 0x1)
771
#define PDM_CLK_PD2 SILABS_DBUS_PDM_CLK(0x3, 0x2)
772
#define PDM_CLK_PD3 SILABS_DBUS_PDM_CLK(0x3, 0x3)
773
#define PDM_DAT0_PA0 SILABS_DBUS_PDM_DAT0(0x0, 0x0)
774
#define PDM_DAT0_PA1 SILABS_DBUS_PDM_DAT0(0x0, 0x1)
775
#define PDM_DAT0_PA2 SILABS_DBUS_PDM_DAT0(0x0, 0x2)
776
#define PDM_DAT0_PA3 SILABS_DBUS_PDM_DAT0(0x0, 0x3)
777
#define PDM_DAT0_PA4 SILABS_DBUS_PDM_DAT0(0x0, 0x4)
778
#define PDM_DAT0_PA5 SILABS_DBUS_PDM_DAT0(0x0, 0x5)
779
#define PDM_DAT0_PA6 SILABS_DBUS_PDM_DAT0(0x0, 0x6)
780
#define PDM_DAT0_PA7 SILABS_DBUS_PDM_DAT0(0x0, 0x7)
781
#define PDM_DAT0_PA8 SILABS_DBUS_PDM_DAT0(0x0, 0x8)
782
#define PDM_DAT0_PB0 SILABS_DBUS_PDM_DAT0(0x1, 0x0)
783
#define PDM_DAT0_PB1 SILABS_DBUS_PDM_DAT0(0x1, 0x1)
784
#define PDM_DAT0_PB2 SILABS_DBUS_PDM_DAT0(0x1, 0x2)
785
#define PDM_DAT0_PB3 SILABS_DBUS_PDM_DAT0(0x1, 0x3)
786
#define PDM_DAT0_PB4 SILABS_DBUS_PDM_DAT0(0x1, 0x4)
787
#define PDM_DAT0_PC0 SILABS_DBUS_PDM_DAT0(0x2, 0x0)
788
#define PDM_DAT0_PC1 SILABS_DBUS_PDM_DAT0(0x2, 0x1)
789
#define PDM_DAT0_PC2 SILABS_DBUS_PDM_DAT0(0x2, 0x2)
790
#define PDM_DAT0_PC3 SILABS_DBUS_PDM_DAT0(0x2, 0x3)
791
#define PDM_DAT0_PC4 SILABS_DBUS_PDM_DAT0(0x2, 0x4)
792
#define PDM_DAT0_PC5 SILABS_DBUS_PDM_DAT0(0x2, 0x5)
793
#define PDM_DAT0_PC6 SILABS_DBUS_PDM_DAT0(0x2, 0x6)
794
#define PDM_DAT0_PC7 SILABS_DBUS_PDM_DAT0(0x2, 0x7)
795
#define PDM_DAT0_PD0 SILABS_DBUS_PDM_DAT0(0x3, 0x0)
796
#define PDM_DAT0_PD1 SILABS_DBUS_PDM_DAT0(0x3, 0x1)
797
#define PDM_DAT0_PD2 SILABS_DBUS_PDM_DAT0(0x3, 0x2)
798
#define PDM_DAT0_PD3 SILABS_DBUS_PDM_DAT0(0x3, 0x3)
799
#define PDM_DAT1_PA0 SILABS_DBUS_PDM_DAT1(0x0, 0x0)
800
#define PDM_DAT1_PA1 SILABS_DBUS_PDM_DAT1(0x0, 0x1)
801
#define PDM_DAT1_PA2 SILABS_DBUS_PDM_DAT1(0x0, 0x2)
802
#define PDM_DAT1_PA3 SILABS_DBUS_PDM_DAT1(0x0, 0x3)
803
#define PDM_DAT1_PA4 SILABS_DBUS_PDM_DAT1(0x0, 0x4)
804
#define PDM_DAT1_PA5 SILABS_DBUS_PDM_DAT1(0x0, 0x5)
805
#define PDM_DAT1_PA6 SILABS_DBUS_PDM_DAT1(0x0, 0x6)
806
#define PDM_DAT1_PA7 SILABS_DBUS_PDM_DAT1(0x0, 0x7)
807
#define PDM_DAT1_PA8 SILABS_DBUS_PDM_DAT1(0x0, 0x8)
808
#define PDM_DAT1_PB0 SILABS_DBUS_PDM_DAT1(0x1, 0x0)
809
#define PDM_DAT1_PB1 SILABS_DBUS_PDM_DAT1(0x1, 0x1)
810
#define PDM_DAT1_PB2 SILABS_DBUS_PDM_DAT1(0x1, 0x2)
811
#define PDM_DAT1_PB3 SILABS_DBUS_PDM_DAT1(0x1, 0x3)
812
#define PDM_DAT1_PB4 SILABS_DBUS_PDM_DAT1(0x1, 0x4)
813
#define PDM_DAT1_PC0 SILABS_DBUS_PDM_DAT1(0x2, 0x0)
814
#define PDM_DAT1_PC1 SILABS_DBUS_PDM_DAT1(0x2, 0x1)
815
#define PDM_DAT1_PC2 SILABS_DBUS_PDM_DAT1(0x2, 0x2)
816
#define PDM_DAT1_PC3 SILABS_DBUS_PDM_DAT1(0x2, 0x3)
817
#define PDM_DAT1_PC4 SILABS_DBUS_PDM_DAT1(0x2, 0x4)
818
#define PDM_DAT1_PC5 SILABS_DBUS_PDM_DAT1(0x2, 0x5)
819
#define PDM_DAT1_PC6 SILABS_DBUS_PDM_DAT1(0x2, 0x6)
820
#define PDM_DAT1_PC7 SILABS_DBUS_PDM_DAT1(0x2, 0x7)
821
#define PDM_DAT1_PD0 SILABS_DBUS_PDM_DAT1(0x3, 0x0)
822
#define PDM_DAT1_PD1 SILABS_DBUS_PDM_DAT1(0x3, 0x1)
823
#define PDM_DAT1_PD2 SILABS_DBUS_PDM_DAT1(0x3, 0x2)
824
#define PDM_DAT1_PD3 SILABS_DBUS_PDM_DAT1(0x3, 0x3)
825
826
#define PRS0_ASYNCH0_PA0 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x0)
827
#define PRS0_ASYNCH0_PA1 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1)
828
#define PRS0_ASYNCH0_PA2 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2)
829
#define PRS0_ASYNCH0_PA3 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3)
830
#define PRS0_ASYNCH0_PA4 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x4)
831
#define PRS0_ASYNCH0_PA5 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5)
832
#define PRS0_ASYNCH0_PA6 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6)
833
#define PRS0_ASYNCH0_PA7 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x7)
834
#define PRS0_ASYNCH0_PA8 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x8)
835
#define PRS0_ASYNCH0_PB0 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0)
836
#define PRS0_ASYNCH0_PB1 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1)
837
#define PRS0_ASYNCH0_PB2 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x2)
838
#define PRS0_ASYNCH0_PB3 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x3)
839
#define PRS0_ASYNCH0_PB4 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x4)
840
#define PRS0_ASYNCH1_PA0 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x0)
841
#define PRS0_ASYNCH1_PA1 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1)
842
#define PRS0_ASYNCH1_PA2 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2)
843
#define PRS0_ASYNCH1_PA3 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3)
844
#define PRS0_ASYNCH1_PA4 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x4)
845
#define PRS0_ASYNCH1_PA5 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5)
846
#define PRS0_ASYNCH1_PA6 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6)
847
#define PRS0_ASYNCH1_PA7 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x7)
848
#define PRS0_ASYNCH1_PA8 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x8)
849
#define PRS0_ASYNCH1_PB0 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0)
850
#define PRS0_ASYNCH1_PB1 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1)
851
#define PRS0_ASYNCH1_PB2 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x2)
852
#define PRS0_ASYNCH1_PB3 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x3)
853
#define PRS0_ASYNCH1_PB4 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x4)
854
#define PRS0_ASYNCH2_PA0 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x0)
855
#define PRS0_ASYNCH2_PA1 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1)
856
#define PRS0_ASYNCH2_PA2 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2)
857
#define PRS0_ASYNCH2_PA3 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3)
858
#define PRS0_ASYNCH2_PA4 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x4)
859
#define PRS0_ASYNCH2_PA5 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5)
860
#define PRS0_ASYNCH2_PA6 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6)
861
#define PRS0_ASYNCH2_PA7 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x7)
862
#define PRS0_ASYNCH2_PA8 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x8)
863
#define PRS0_ASYNCH2_PB0 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0)
864
#define PRS0_ASYNCH2_PB1 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1)
865
#define PRS0_ASYNCH2_PB2 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x2)
866
#define PRS0_ASYNCH2_PB3 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x3)
867
#define PRS0_ASYNCH2_PB4 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x4)
868
#define PRS0_ASYNCH3_PA0 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x0)
869
#define PRS0_ASYNCH3_PA1 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1)
870
#define PRS0_ASYNCH3_PA2 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2)
871
#define PRS0_ASYNCH3_PA3 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3)
872
#define PRS0_ASYNCH3_PA4 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x4)
873
#define PRS0_ASYNCH3_PA5 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5)
874
#define PRS0_ASYNCH3_PA6 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6)
875
#define PRS0_ASYNCH3_PA7 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x7)
876
#define PRS0_ASYNCH3_PA8 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x8)
877
#define PRS0_ASYNCH3_PB0 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0)
878
#define PRS0_ASYNCH3_PB1 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1)
879
#define PRS0_ASYNCH3_PB2 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x2)
880
#define PRS0_ASYNCH3_PB3 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x3)
881
#define PRS0_ASYNCH3_PB4 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x4)
882
#define PRS0_ASYNCH4_PA0 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x0)
883
#define PRS0_ASYNCH4_PA1 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1)
884
#define PRS0_ASYNCH4_PA2 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2)
885
#define PRS0_ASYNCH4_PA3 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3)
886
#define PRS0_ASYNCH4_PA4 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x4)
887
#define PRS0_ASYNCH4_PA5 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5)
888
#define PRS0_ASYNCH4_PA6 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6)
889
#define PRS0_ASYNCH4_PA7 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x7)
890
#define PRS0_ASYNCH4_PA8 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x8)
891
#define PRS0_ASYNCH4_PB0 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0)
892
#define PRS0_ASYNCH4_PB1 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1)
893
#define PRS0_ASYNCH4_PB2 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x2)
894
#define PRS0_ASYNCH4_PB3 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x3)
895
#define PRS0_ASYNCH4_PB4 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x4)
896
#define PRS0_ASYNCH5_PA0 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x0)
897
#define PRS0_ASYNCH5_PA1 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1)
898
#define PRS0_ASYNCH5_PA2 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2)
899
#define PRS0_ASYNCH5_PA3 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3)
900
#define PRS0_ASYNCH5_PA4 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x4)
901
#define PRS0_ASYNCH5_PA5 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5)
902
#define PRS0_ASYNCH5_PA6 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6)
903
#define PRS0_ASYNCH5_PA7 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x7)
904
#define PRS0_ASYNCH5_PA8 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x8)
905
#define PRS0_ASYNCH5_PB0 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0)
906
#define PRS0_ASYNCH5_PB1 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1)
907
#define PRS0_ASYNCH5_PB2 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x2)
908
#define PRS0_ASYNCH5_PB3 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x3)
909
#define PRS0_ASYNCH5_PB4 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x4)
910
#define PRS0_ASYNCH6_PC0 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0)
911
#define PRS0_ASYNCH6_PC1 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1)
912
#define PRS0_ASYNCH6_PC2 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2)
913
#define PRS0_ASYNCH6_PC3 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3)
914
#define PRS0_ASYNCH6_PC4 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4)
915
#define PRS0_ASYNCH6_PC5 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5)
916
#define PRS0_ASYNCH6_PC6 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x6)
917
#define PRS0_ASYNCH6_PC7 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x7)
918
#define PRS0_ASYNCH6_PD0 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0)
919
#define PRS0_ASYNCH6_PD1 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1)
920
#define PRS0_ASYNCH6_PD2 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2)
921
#define PRS0_ASYNCH6_PD3 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3)
922
#define PRS0_ASYNCH7_PC0 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0)
923
#define PRS0_ASYNCH7_PC1 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1)
924
#define PRS0_ASYNCH7_PC2 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2)
925
#define PRS0_ASYNCH7_PC3 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3)
926
#define PRS0_ASYNCH7_PC4 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4)
927
#define PRS0_ASYNCH7_PC5 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5)
928
#define PRS0_ASYNCH7_PC6 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x6)
929
#define PRS0_ASYNCH7_PC7 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x7)
930
#define PRS0_ASYNCH7_PD0 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0)
931
#define PRS0_ASYNCH7_PD1 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1)
932
#define PRS0_ASYNCH7_PD2 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2)
933
#define PRS0_ASYNCH7_PD3 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3)
934
#define PRS0_ASYNCH8_PC0 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0)
935
#define PRS0_ASYNCH8_PC1 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1)
936
#define PRS0_ASYNCH8_PC2 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2)
937
#define PRS0_ASYNCH8_PC3 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3)
938
#define PRS0_ASYNCH8_PC4 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4)
939
#define PRS0_ASYNCH8_PC5 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5)
940
#define PRS0_ASYNCH8_PC6 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x6)
941
#define PRS0_ASYNCH8_PC7 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x7)
942
#define PRS0_ASYNCH8_PD0 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0)
943
#define PRS0_ASYNCH8_PD1 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1)
944
#define PRS0_ASYNCH8_PD2 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2)
945
#define PRS0_ASYNCH8_PD3 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3)
946
#define PRS0_ASYNCH9_PC0 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0)
947
#define PRS0_ASYNCH9_PC1 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1)
948
#define PRS0_ASYNCH9_PC2 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2)
949
#define PRS0_ASYNCH9_PC3 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3)
950
#define PRS0_ASYNCH9_PC4 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4)
951
#define PRS0_ASYNCH9_PC5 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5)
952
#define PRS0_ASYNCH9_PC6 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x6)
953
#define PRS0_ASYNCH9_PC7 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x7)
954
#define PRS0_ASYNCH9_PD0 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0)
955
#define PRS0_ASYNCH9_PD1 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1)
956
#define PRS0_ASYNCH9_PD2 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2)
957
#define PRS0_ASYNCH9_PD3 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3)
958
#define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0)
959
#define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1)
960
#define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2)
961
#define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3)
962
#define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4)
963
#define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5)
964
#define PRS0_ASYNCH10_PC6 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x6)
965
#define PRS0_ASYNCH10_PC7 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x7)
966
#define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0)
967
#define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1)
968
#define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2)
969
#define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3)
970
#define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0)
971
#define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1)
972
#define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2)
973
#define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3)
974
#define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4)
975
#define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5)
976
#define PRS0_ASYNCH11_PC6 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x6)
977
#define PRS0_ASYNCH11_PC7 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x7)
978
#define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0)
979
#define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1)
980
#define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2)
981
#define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3)
982
#define PRS0_SYNCH0_PA0 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x0)
983
#define PRS0_SYNCH0_PA1 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1)
984
#define PRS0_SYNCH0_PA2 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2)
985
#define PRS0_SYNCH0_PA3 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3)
986
#define PRS0_SYNCH0_PA4 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x4)
987
#define PRS0_SYNCH0_PA5 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5)
988
#define PRS0_SYNCH0_PA6 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6)
989
#define PRS0_SYNCH0_PA7 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x7)
990
#define PRS0_SYNCH0_PA8 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x8)
991
#define PRS0_SYNCH0_PB0 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0)
992
#define PRS0_SYNCH0_PB1 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1)
993
#define PRS0_SYNCH0_PB2 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x2)
994
#define PRS0_SYNCH0_PB3 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x3)
995
#define PRS0_SYNCH0_PB4 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x4)
996
#define PRS0_SYNCH0_PC0 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0)
997
#define PRS0_SYNCH0_PC1 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1)
998
#define PRS0_SYNCH0_PC2 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2)
999
#define PRS0_SYNCH0_PC3 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3)
1000
#define PRS0_SYNCH0_PC4 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4)
1001
#define PRS0_SYNCH0_PC5 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5)
1002
#define PRS0_SYNCH0_PC6 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x6)
1003
#define PRS0_SYNCH0_PC7 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x7)
1004
#define PRS0_SYNCH0_PD0 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0)
1005
#define PRS0_SYNCH0_PD1 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1)
1006
#define PRS0_SYNCH0_PD2 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2)
1007
#define PRS0_SYNCH0_PD3 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3)
1008
#define PRS0_SYNCH1_PA0 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x0)
1009
#define PRS0_SYNCH1_PA1 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1)
1010
#define PRS0_SYNCH1_PA2 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2)
1011
#define PRS0_SYNCH1_PA3 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3)
1012
#define PRS0_SYNCH1_PA4 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x4)
1013
#define PRS0_SYNCH1_PA5 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5)
1014
#define PRS0_SYNCH1_PA6 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6)
1015
#define PRS0_SYNCH1_PA7 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x7)
1016
#define PRS0_SYNCH1_PA8 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x8)
1017
#define PRS0_SYNCH1_PB0 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0)
1018
#define PRS0_SYNCH1_PB1 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1)
1019
#define PRS0_SYNCH1_PB2 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x2)
1020
#define PRS0_SYNCH1_PB3 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x3)
1021
#define PRS0_SYNCH1_PB4 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x4)
1022
#define PRS0_SYNCH1_PC0 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0)
1023
#define PRS0_SYNCH1_PC1 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1)
1024
#define PRS0_SYNCH1_PC2 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2)
1025
#define PRS0_SYNCH1_PC3 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3)
1026
#define PRS0_SYNCH1_PC4 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4)
1027
#define PRS0_SYNCH1_PC5 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5)
1028
#define PRS0_SYNCH1_PC6 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x6)
1029
#define PRS0_SYNCH1_PC7 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x7)
1030
#define PRS0_SYNCH1_PD0 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0)
1031
#define PRS0_SYNCH1_PD1 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1)
1032
#define PRS0_SYNCH1_PD2 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2)
1033
#define PRS0_SYNCH1_PD3 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3)
1034
#define PRS0_SYNCH2_PA0 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x0)
1035
#define PRS0_SYNCH2_PA1 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1)
1036
#define PRS0_SYNCH2_PA2 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2)
1037
#define PRS0_SYNCH2_PA3 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3)
1038
#define PRS0_SYNCH2_PA4 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x4)
1039
#define PRS0_SYNCH2_PA5 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5)
1040
#define PRS0_SYNCH2_PA6 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6)
1041
#define PRS0_SYNCH2_PA7 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x7)
1042
#define PRS0_SYNCH2_PA8 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x8)
1043
#define PRS0_SYNCH2_PB0 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0)
1044
#define PRS0_SYNCH2_PB1 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1)
1045
#define PRS0_SYNCH2_PB2 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x2)
1046
#define PRS0_SYNCH2_PB3 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x3)
1047
#define PRS0_SYNCH2_PB4 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x4)
1048
#define PRS0_SYNCH2_PC0 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0)
1049
#define PRS0_SYNCH2_PC1 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1)
1050
#define PRS0_SYNCH2_PC2 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2)
1051
#define PRS0_SYNCH2_PC3 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3)
1052
#define PRS0_SYNCH2_PC4 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4)
1053
#define PRS0_SYNCH2_PC5 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5)
1054
#define PRS0_SYNCH2_PC6 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x6)
1055
#define PRS0_SYNCH2_PC7 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x7)
1056
#define PRS0_SYNCH2_PD0 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0)
1057
#define PRS0_SYNCH2_PD1 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1)
1058
#define PRS0_SYNCH2_PD2 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2)
1059
#define PRS0_SYNCH2_PD3 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3)
1060
#define PRS0_SYNCH3_PA0 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x0)
1061
#define PRS0_SYNCH3_PA1 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1)
1062
#define PRS0_SYNCH3_PA2 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2)
1063
#define PRS0_SYNCH3_PA3 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3)
1064
#define PRS0_SYNCH3_PA4 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x4)
1065
#define PRS0_SYNCH3_PA5 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5)
1066
#define PRS0_SYNCH3_PA6 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6)
1067
#define PRS0_SYNCH3_PA7 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x7)
1068
#define PRS0_SYNCH3_PA8 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x8)
1069
#define PRS0_SYNCH3_PB0 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0)
1070
#define PRS0_SYNCH3_PB1 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1)
1071
#define PRS0_SYNCH3_PB2 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x2)
1072
#define PRS0_SYNCH3_PB3 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x3)
1073
#define PRS0_SYNCH3_PB4 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x4)
1074
#define PRS0_SYNCH3_PC0 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0)
1075
#define PRS0_SYNCH3_PC1 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1)
1076
#define PRS0_SYNCH3_PC2 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2)
1077
#define PRS0_SYNCH3_PC3 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3)
1078
#define PRS0_SYNCH3_PC4 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4)
1079
#define PRS0_SYNCH3_PC5 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5)
1080
#define PRS0_SYNCH3_PC6 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x6)
1081
#define PRS0_SYNCH3_PC7 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x7)
1082
#define PRS0_SYNCH3_PD0 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0)
1083
#define PRS0_SYNCH3_PD1 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1)
1084
#define PRS0_SYNCH3_PD2 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2)
1085
#define PRS0_SYNCH3_PD3 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3)
1086
1087
#define TIMER0_CC0_PA0 SILABS_DBUS_TIMER0_CC0(0x0, 0x0)
1088
#define TIMER0_CC0_PA1 SILABS_DBUS_TIMER0_CC0(0x0, 0x1)
1089
#define TIMER0_CC0_PA2 SILABS_DBUS_TIMER0_CC0(0x0, 0x2)
1090
#define TIMER0_CC0_PA3 SILABS_DBUS_TIMER0_CC0(0x0, 0x3)
1091
#define TIMER0_CC0_PA4 SILABS_DBUS_TIMER0_CC0(0x0, 0x4)
1092
#define TIMER0_CC0_PA5 SILABS_DBUS_TIMER0_CC0(0x0, 0x5)
1093
#define TIMER0_CC0_PA6 SILABS_DBUS_TIMER0_CC0(0x0, 0x6)
1094
#define TIMER0_CC0_PA7 SILABS_DBUS_TIMER0_CC0(0x0, 0x7)
1095
#define TIMER0_CC0_PA8 SILABS_DBUS_TIMER0_CC0(0x0, 0x8)
1096
#define TIMER0_CC0_PB0 SILABS_DBUS_TIMER0_CC0(0x1, 0x0)
1097
#define TIMER0_CC0_PB1 SILABS_DBUS_TIMER0_CC0(0x1, 0x1)
1098
#define TIMER0_CC0_PB2 SILABS_DBUS_TIMER0_CC0(0x1, 0x2)
1099
#define TIMER0_CC0_PB3 SILABS_DBUS_TIMER0_CC0(0x1, 0x3)
1100
#define TIMER0_CC0_PB4 SILABS_DBUS_TIMER0_CC0(0x1, 0x4)
1101
#define TIMER0_CC0_PC0 SILABS_DBUS_TIMER0_CC0(0x2, 0x0)
1102
#define TIMER0_CC0_PC1 SILABS_DBUS_TIMER0_CC0(0x2, 0x1)
1103
#define TIMER0_CC0_PC2 SILABS_DBUS_TIMER0_CC0(0x2, 0x2)
1104
#define TIMER0_CC0_PC3 SILABS_DBUS_TIMER0_CC0(0x2, 0x3)
1105
#define TIMER0_CC0_PC4 SILABS_DBUS_TIMER0_CC0(0x2, 0x4)
1106
#define TIMER0_CC0_PC5 SILABS_DBUS_TIMER0_CC0(0x2, 0x5)
1107
#define TIMER0_CC0_PC6 SILABS_DBUS_TIMER0_CC0(0x2, 0x6)
1108
#define TIMER0_CC0_PC7 SILABS_DBUS_TIMER0_CC0(0x2, 0x7)
1109
#define TIMER0_CC0_PD0 SILABS_DBUS_TIMER0_CC0(0x3, 0x0)
1110
#define TIMER0_CC0_PD1 SILABS_DBUS_TIMER0_CC0(0x3, 0x1)
1111
#define TIMER0_CC0_PD2 SILABS_DBUS_TIMER0_CC0(0x3, 0x2)
1112
#define TIMER0_CC0_PD3 SILABS_DBUS_TIMER0_CC0(0x3, 0x3)
1113
#define TIMER0_CC1_PA0 SILABS_DBUS_TIMER0_CC1(0x0, 0x0)
1114
#define TIMER0_CC1_PA1 SILABS_DBUS_TIMER0_CC1(0x0, 0x1)
1115
#define TIMER0_CC1_PA2 SILABS_DBUS_TIMER0_CC1(0x0, 0x2)
1116
#define TIMER0_CC1_PA3 SILABS_DBUS_TIMER0_CC1(0x0, 0x3)
1117
#define TIMER0_CC1_PA4 SILABS_DBUS_TIMER0_CC1(0x0, 0x4)
1118
#define TIMER0_CC1_PA5 SILABS_DBUS_TIMER0_CC1(0x0, 0x5)
1119
#define TIMER0_CC1_PA6 SILABS_DBUS_TIMER0_CC1(0x0, 0x6)
1120
#define TIMER0_CC1_PA7 SILABS_DBUS_TIMER0_CC1(0x0, 0x7)
1121
#define TIMER0_CC1_PA8 SILABS_DBUS_TIMER0_CC1(0x0, 0x8)
1122
#define TIMER0_CC1_PB0 SILABS_DBUS_TIMER0_CC1(0x1, 0x0)
1123
#define TIMER0_CC1_PB1 SILABS_DBUS_TIMER0_CC1(0x1, 0x1)
1124
#define TIMER0_CC1_PB2 SILABS_DBUS_TIMER0_CC1(0x1, 0x2)
1125
#define TIMER0_CC1_PB3 SILABS_DBUS_TIMER0_CC1(0x1, 0x3)
1126
#define TIMER0_CC1_PB4 SILABS_DBUS_TIMER0_CC1(0x1, 0x4)
1127
#define TIMER0_CC1_PC0 SILABS_DBUS_TIMER0_CC1(0x2, 0x0)
1128
#define TIMER0_CC1_PC1 SILABS_DBUS_TIMER0_CC1(0x2, 0x1)
1129
#define TIMER0_CC1_PC2 SILABS_DBUS_TIMER0_CC1(0x2, 0x2)
1130
#define TIMER0_CC1_PC3 SILABS_DBUS_TIMER0_CC1(0x2, 0x3)
1131
#define TIMER0_CC1_PC4 SILABS_DBUS_TIMER0_CC1(0x2, 0x4)
1132
#define TIMER0_CC1_PC5 SILABS_DBUS_TIMER0_CC1(0x2, 0x5)
1133
#define TIMER0_CC1_PC6 SILABS_DBUS_TIMER0_CC1(0x2, 0x6)
1134
#define TIMER0_CC1_PC7 SILABS_DBUS_TIMER0_CC1(0x2, 0x7)
1135
#define TIMER0_CC1_PD0 SILABS_DBUS_TIMER0_CC1(0x3, 0x0)
1136
#define TIMER0_CC1_PD1 SILABS_DBUS_TIMER0_CC1(0x3, 0x1)
1137
#define TIMER0_CC1_PD2 SILABS_DBUS_TIMER0_CC1(0x3, 0x2)
1138
#define TIMER0_CC1_PD3 SILABS_DBUS_TIMER0_CC1(0x3, 0x3)
1139
#define TIMER0_CC2_PA0 SILABS_DBUS_TIMER0_CC2(0x0, 0x0)
1140
#define TIMER0_CC2_PA1 SILABS_DBUS_TIMER0_CC2(0x0, 0x1)
1141
#define TIMER0_CC2_PA2 SILABS_DBUS_TIMER0_CC2(0x0, 0x2)
1142
#define TIMER0_CC2_PA3 SILABS_DBUS_TIMER0_CC2(0x0, 0x3)
1143
#define TIMER0_CC2_PA4 SILABS_DBUS_TIMER0_CC2(0x0, 0x4)
1144
#define TIMER0_CC2_PA5 SILABS_DBUS_TIMER0_CC2(0x0, 0x5)
1145
#define TIMER0_CC2_PA6 SILABS_DBUS_TIMER0_CC2(0x0, 0x6)
1146
#define TIMER0_CC2_PA7 SILABS_DBUS_TIMER0_CC2(0x0, 0x7)
1147
#define TIMER0_CC2_PA8 SILABS_DBUS_TIMER0_CC2(0x0, 0x8)
1148
#define TIMER0_CC2_PB0 SILABS_DBUS_TIMER0_CC2(0x1, 0x0)
1149
#define TIMER0_CC2_PB1 SILABS_DBUS_TIMER0_CC2(0x1, 0x1)
1150
#define TIMER0_CC2_PB2 SILABS_DBUS_TIMER0_CC2(0x1, 0x2)
1151
#define TIMER0_CC2_PB3 SILABS_DBUS_TIMER0_CC2(0x1, 0x3)
1152
#define TIMER0_CC2_PB4 SILABS_DBUS_TIMER0_CC2(0x1, 0x4)
1153
#define TIMER0_CC2_PC0 SILABS_DBUS_TIMER0_CC2(0x2, 0x0)
1154
#define TIMER0_CC2_PC1 SILABS_DBUS_TIMER0_CC2(0x2, 0x1)
1155
#define TIMER0_CC2_PC2 SILABS_DBUS_TIMER0_CC2(0x2, 0x2)
1156
#define TIMER0_CC2_PC3 SILABS_DBUS_TIMER0_CC2(0x2, 0x3)
1157
#define TIMER0_CC2_PC4 SILABS_DBUS_TIMER0_CC2(0x2, 0x4)
1158
#define TIMER0_CC2_PC5 SILABS_DBUS_TIMER0_CC2(0x2, 0x5)
1159
#define TIMER0_CC2_PC6 SILABS_DBUS_TIMER0_CC2(0x2, 0x6)
1160
#define TIMER0_CC2_PC7 SILABS_DBUS_TIMER0_CC2(0x2, 0x7)
1161
#define TIMER0_CC2_PD0 SILABS_DBUS_TIMER0_CC2(0x3, 0x0)
1162
#define TIMER0_CC2_PD1 SILABS_DBUS_TIMER0_CC2(0x3, 0x1)
1163
#define TIMER0_CC2_PD2 SILABS_DBUS_TIMER0_CC2(0x3, 0x2)
1164
#define TIMER0_CC2_PD3 SILABS_DBUS_TIMER0_CC2(0x3, 0x3)
1165
#define TIMER0_CDTI0_PA0 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x0)
1166
#define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1)
1167
#define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2)
1168
#define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3)
1169
#define TIMER0_CDTI0_PA4 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x4)
1170
#define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5)
1171
#define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6)
1172
#define TIMER0_CDTI0_PA7 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x7)
1173
#define TIMER0_CDTI0_PA8 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x8)
1174
#define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0)
1175
#define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1)
1176
#define TIMER0_CDTI0_PB2 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x2)
1177
#define TIMER0_CDTI0_PB3 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x3)
1178
#define TIMER0_CDTI0_PB4 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x4)
1179
#define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0)
1180
#define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1)
1181
#define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2)
1182
#define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3)
1183
#define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4)
1184
#define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5)
1185
#define TIMER0_CDTI0_PC6 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x6)
1186
#define TIMER0_CDTI0_PC7 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x7)
1187
#define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0)
1188
#define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1)
1189
#define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2)
1190
#define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3)
1191
#define TIMER0_CDTI1_PA0 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x0)
1192
#define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1)
1193
#define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2)
1194
#define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3)
1195
#define TIMER0_CDTI1_PA4 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x4)
1196
#define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5)
1197
#define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6)
1198
#define TIMER0_CDTI1_PA7 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x7)
1199
#define TIMER0_CDTI1_PA8 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x8)
1200
#define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0)
1201
#define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1)
1202
#define TIMER0_CDTI1_PB2 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x2)
1203
#define TIMER0_CDTI1_PB3 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x3)
1204
#define TIMER0_CDTI1_PB4 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x4)
1205
#define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0)
1206
#define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1)
1207
#define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2)
1208
#define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3)
1209
#define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4)
1210
#define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5)
1211
#define TIMER0_CDTI1_PC6 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x6)
1212
#define TIMER0_CDTI1_PC7 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x7)
1213
#define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0)
1214
#define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1)
1215
#define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2)
1216
#define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3)
1217
#define TIMER0_CDTI2_PA0 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x0)
1218
#define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1)
1219
#define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2)
1220
#define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3)
1221
#define TIMER0_CDTI2_PA4 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x4)
1222
#define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5)
1223
#define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6)
1224
#define TIMER0_CDTI2_PA7 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x7)
1225
#define TIMER0_CDTI2_PA8 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x8)
1226
#define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0)
1227
#define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1)
1228
#define TIMER0_CDTI2_PB2 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x2)
1229
#define TIMER0_CDTI2_PB3 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x3)
1230
#define TIMER0_CDTI2_PB4 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x4)
1231
#define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0)
1232
#define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1)
1233
#define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2)
1234
#define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3)
1235
#define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4)
1236
#define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5)
1237
#define TIMER0_CDTI2_PC6 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x6)
1238
#define TIMER0_CDTI2_PC7 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x7)
1239
#define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0)
1240
#define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1)
1241
#define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2)
1242
#define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3)
1243
1244
#define TIMER1_CC0_PA0 SILABS_DBUS_TIMER1_CC0(0x0, 0x0)
1245
#define TIMER1_CC0_PA1 SILABS_DBUS_TIMER1_CC0(0x0, 0x1)
1246
#define TIMER1_CC0_PA2 SILABS_DBUS_TIMER1_CC0(0x0, 0x2)
1247
#define TIMER1_CC0_PA3 SILABS_DBUS_TIMER1_CC0(0x0, 0x3)
1248
#define TIMER1_CC0_PA4 SILABS_DBUS_TIMER1_CC0(0x0, 0x4)
1249
#define TIMER1_CC0_PA5 SILABS_DBUS_TIMER1_CC0(0x0, 0x5)
1250
#define TIMER1_CC0_PA6 SILABS_DBUS_TIMER1_CC0(0x0, 0x6)
1251
#define TIMER1_CC0_PA7 SILABS_DBUS_TIMER1_CC0(0x0, 0x7)
1252
#define TIMER1_CC0_PA8 SILABS_DBUS_TIMER1_CC0(0x0, 0x8)
1253
#define TIMER1_CC0_PB0 SILABS_DBUS_TIMER1_CC0(0x1, 0x0)
1254
#define TIMER1_CC0_PB1 SILABS_DBUS_TIMER1_CC0(0x1, 0x1)
1255
#define TIMER1_CC0_PB2 SILABS_DBUS_TIMER1_CC0(0x1, 0x2)
1256
#define TIMER1_CC0_PB3 SILABS_DBUS_TIMER1_CC0(0x1, 0x3)
1257
#define TIMER1_CC0_PB4 SILABS_DBUS_TIMER1_CC0(0x1, 0x4)
1258
#define TIMER1_CC0_PC0 SILABS_DBUS_TIMER1_CC0(0x2, 0x0)
1259
#define TIMER1_CC0_PC1 SILABS_DBUS_TIMER1_CC0(0x2, 0x1)
1260
#define TIMER1_CC0_PC2 SILABS_DBUS_TIMER1_CC0(0x2, 0x2)
1261
#define TIMER1_CC0_PC3 SILABS_DBUS_TIMER1_CC0(0x2, 0x3)
1262
#define TIMER1_CC0_PC4 SILABS_DBUS_TIMER1_CC0(0x2, 0x4)
1263
#define TIMER1_CC0_PC5 SILABS_DBUS_TIMER1_CC0(0x2, 0x5)
1264
#define TIMER1_CC0_PC6 SILABS_DBUS_TIMER1_CC0(0x2, 0x6)
1265
#define TIMER1_CC0_PC7 SILABS_DBUS_TIMER1_CC0(0x2, 0x7)
1266
#define TIMER1_CC0_PD0 SILABS_DBUS_TIMER1_CC0(0x3, 0x0)
1267
#define TIMER1_CC0_PD1 SILABS_DBUS_TIMER1_CC0(0x3, 0x1)
1268
#define TIMER1_CC0_PD2 SILABS_DBUS_TIMER1_CC0(0x3, 0x2)
1269
#define TIMER1_CC0_PD3 SILABS_DBUS_TIMER1_CC0(0x3, 0x3)
1270
#define TIMER1_CC1_PA0 SILABS_DBUS_TIMER1_CC1(0x0, 0x0)
1271
#define TIMER1_CC1_PA1 SILABS_DBUS_TIMER1_CC1(0x0, 0x1)
1272
#define TIMER1_CC1_PA2 SILABS_DBUS_TIMER1_CC1(0x0, 0x2)
1273
#define TIMER1_CC1_PA3 SILABS_DBUS_TIMER1_CC1(0x0, 0x3)
1274
#define TIMER1_CC1_PA4 SILABS_DBUS_TIMER1_CC1(0x0, 0x4)
1275
#define TIMER1_CC1_PA5 SILABS_DBUS_TIMER1_CC1(0x0, 0x5)
1276
#define TIMER1_CC1_PA6 SILABS_DBUS_TIMER1_CC1(0x0, 0x6)
1277
#define TIMER1_CC1_PA7 SILABS_DBUS_TIMER1_CC1(0x0, 0x7)
1278
#define TIMER1_CC1_PA8 SILABS_DBUS_TIMER1_CC1(0x0, 0x8)
1279
#define TIMER1_CC1_PB0 SILABS_DBUS_TIMER1_CC1(0x1, 0x0)
1280
#define TIMER1_CC1_PB1 SILABS_DBUS_TIMER1_CC1(0x1, 0x1)
1281
#define TIMER1_CC1_PB2 SILABS_DBUS_TIMER1_CC1(0x1, 0x2)
1282
#define TIMER1_CC1_PB3 SILABS_DBUS_TIMER1_CC1(0x1, 0x3)
1283
#define TIMER1_CC1_PB4 SILABS_DBUS_TIMER1_CC1(0x1, 0x4)
1284
#define TIMER1_CC1_PC0 SILABS_DBUS_TIMER1_CC1(0x2, 0x0)
1285
#define TIMER1_CC1_PC1 SILABS_DBUS_TIMER1_CC1(0x2, 0x1)
1286
#define TIMER1_CC1_PC2 SILABS_DBUS_TIMER1_CC1(0x2, 0x2)
1287
#define TIMER1_CC1_PC3 SILABS_DBUS_TIMER1_CC1(0x2, 0x3)
1288
#define TIMER1_CC1_PC4 SILABS_DBUS_TIMER1_CC1(0x2, 0x4)
1289
#define TIMER1_CC1_PC5 SILABS_DBUS_TIMER1_CC1(0x2, 0x5)
1290
#define TIMER1_CC1_PC6 SILABS_DBUS_TIMER1_CC1(0x2, 0x6)
1291
#define TIMER1_CC1_PC7 SILABS_DBUS_TIMER1_CC1(0x2, 0x7)
1292
#define TIMER1_CC1_PD0 SILABS_DBUS_TIMER1_CC1(0x3, 0x0)
1293
#define TIMER1_CC1_PD1 SILABS_DBUS_TIMER1_CC1(0x3, 0x1)
1294
#define TIMER1_CC1_PD2 SILABS_DBUS_TIMER1_CC1(0x3, 0x2)
1295
#define TIMER1_CC1_PD3 SILABS_DBUS_TIMER1_CC1(0x3, 0x3)
1296
#define TIMER1_CC2_PA0 SILABS_DBUS_TIMER1_CC2(0x0, 0x0)
1297
#define TIMER1_CC2_PA1 SILABS_DBUS_TIMER1_CC2(0x0, 0x1)
1298
#define TIMER1_CC2_PA2 SILABS_DBUS_TIMER1_CC2(0x0, 0x2)
1299
#define TIMER1_CC2_PA3 SILABS_DBUS_TIMER1_CC2(0x0, 0x3)
1300
#define TIMER1_CC2_PA4 SILABS_DBUS_TIMER1_CC2(0x0, 0x4)
1301
#define TIMER1_CC2_PA5 SILABS_DBUS_TIMER1_CC2(0x0, 0x5)
1302
#define TIMER1_CC2_PA6 SILABS_DBUS_TIMER1_CC2(0x0, 0x6)
1303
#define TIMER1_CC2_PA7 SILABS_DBUS_TIMER1_CC2(0x0, 0x7)
1304
#define TIMER1_CC2_PA8 SILABS_DBUS_TIMER1_CC2(0x0, 0x8)
1305
#define TIMER1_CC2_PB0 SILABS_DBUS_TIMER1_CC2(0x1, 0x0)
1306
#define TIMER1_CC2_PB1 SILABS_DBUS_TIMER1_CC2(0x1, 0x1)
1307
#define TIMER1_CC2_PB2 SILABS_DBUS_TIMER1_CC2(0x1, 0x2)
1308
#define TIMER1_CC2_PB3 SILABS_DBUS_TIMER1_CC2(0x1, 0x3)
1309
#define TIMER1_CC2_PB4 SILABS_DBUS_TIMER1_CC2(0x1, 0x4)
1310
#define TIMER1_CC2_PC0 SILABS_DBUS_TIMER1_CC2(0x2, 0x0)
1311
#define TIMER1_CC2_PC1 SILABS_DBUS_TIMER1_CC2(0x2, 0x1)
1312
#define TIMER1_CC2_PC2 SILABS_DBUS_TIMER1_CC2(0x2, 0x2)
1313
#define TIMER1_CC2_PC3 SILABS_DBUS_TIMER1_CC2(0x2, 0x3)
1314
#define TIMER1_CC2_PC4 SILABS_DBUS_TIMER1_CC2(0x2, 0x4)
1315
#define TIMER1_CC2_PC5 SILABS_DBUS_TIMER1_CC2(0x2, 0x5)
1316
#define TIMER1_CC2_PC6 SILABS_DBUS_TIMER1_CC2(0x2, 0x6)
1317
#define TIMER1_CC2_PC7 SILABS_DBUS_TIMER1_CC2(0x2, 0x7)
1318
#define TIMER1_CC2_PD0 SILABS_DBUS_TIMER1_CC2(0x3, 0x0)
1319
#define TIMER1_CC2_PD1 SILABS_DBUS_TIMER1_CC2(0x3, 0x1)
1320
#define TIMER1_CC2_PD2 SILABS_DBUS_TIMER1_CC2(0x3, 0x2)
1321
#define TIMER1_CC2_PD3 SILABS_DBUS_TIMER1_CC2(0x3, 0x3)
1322
#define TIMER1_CDTI0_PA0 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x0)
1323
#define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1)
1324
#define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2)
1325
#define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3)
1326
#define TIMER1_CDTI0_PA4 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x4)
1327
#define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5)
1328
#define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6)
1329
#define TIMER1_CDTI0_PA7 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x7)
1330
#define TIMER1_CDTI0_PA8 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x8)
1331
#define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0)
1332
#define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1)
1333
#define TIMER1_CDTI0_PB2 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x2)
1334
#define TIMER1_CDTI0_PB3 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x3)
1335
#define TIMER1_CDTI0_PB4 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x4)
1336
#define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0)
1337
#define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1)
1338
#define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2)
1339
#define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3)
1340
#define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4)
1341
#define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5)
1342
#define TIMER1_CDTI0_PC6 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x6)
1343
#define TIMER1_CDTI0_PC7 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x7)
1344
#define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0)
1345
#define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1)
1346
#define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2)
1347
#define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3)
1348
#define TIMER1_CDTI1_PA0 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x0)
1349
#define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1)
1350
#define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2)
1351
#define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3)
1352
#define TIMER1_CDTI1_PA4 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x4)
1353
#define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5)
1354
#define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6)
1355
#define TIMER1_CDTI1_PA7 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x7)
1356
#define TIMER1_CDTI1_PA8 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x8)
1357
#define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0)
1358
#define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1)
1359
#define TIMER1_CDTI1_PB2 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x2)
1360
#define TIMER1_CDTI1_PB3 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x3)
1361
#define TIMER1_CDTI1_PB4 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x4)
1362
#define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0)
1363
#define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1)
1364
#define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2)
1365
#define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3)
1366
#define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4)
1367
#define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5)
1368
#define TIMER1_CDTI1_PC6 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x6)
1369
#define TIMER1_CDTI1_PC7 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x7)
1370
#define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0)
1371
#define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1)
1372
#define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2)
1373
#define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3)
1374
#define TIMER1_CDTI2_PA0 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x0)
1375
#define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1)
1376
#define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2)
1377
#define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3)
1378
#define TIMER1_CDTI2_PA4 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x4)
1379
#define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5)
1380
#define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6)
1381
#define TIMER1_CDTI2_PA7 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x7)
1382
#define TIMER1_CDTI2_PA8 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x8)
1383
#define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0)
1384
#define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1)
1385
#define TIMER1_CDTI2_PB2 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x2)
1386
#define TIMER1_CDTI2_PB3 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x3)
1387
#define TIMER1_CDTI2_PB4 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x4)
1388
#define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0)
1389
#define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1)
1390
#define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2)
1391
#define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3)
1392
#define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4)
1393
#define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5)
1394
#define TIMER1_CDTI2_PC6 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x6)
1395
#define TIMER1_CDTI2_PC7 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x7)
1396
#define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0)
1397
#define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1)
1398
#define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2)
1399
#define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3)
1400
1401
#define TIMER2_CC0_PA0 SILABS_DBUS_TIMER2_CC0(0x0, 0x0)
1402
#define TIMER2_CC0_PA1 SILABS_DBUS_TIMER2_CC0(0x0, 0x1)
1403
#define TIMER2_CC0_PA2 SILABS_DBUS_TIMER2_CC0(0x0, 0x2)
1404
#define TIMER2_CC0_PA3 SILABS_DBUS_TIMER2_CC0(0x0, 0x3)
1405
#define TIMER2_CC0_PA4 SILABS_DBUS_TIMER2_CC0(0x0, 0x4)
1406
#define TIMER2_CC0_PA5 SILABS_DBUS_TIMER2_CC0(0x0, 0x5)
1407
#define TIMER2_CC0_PA6 SILABS_DBUS_TIMER2_CC0(0x0, 0x6)
1408
#define TIMER2_CC0_PA7 SILABS_DBUS_TIMER2_CC0(0x0, 0x7)
1409
#define TIMER2_CC0_PA8 SILABS_DBUS_TIMER2_CC0(0x0, 0x8)
1410
#define TIMER2_CC0_PB0 SILABS_DBUS_TIMER2_CC0(0x1, 0x0)
1411
#define TIMER2_CC0_PB1 SILABS_DBUS_TIMER2_CC0(0x1, 0x1)
1412
#define TIMER2_CC0_PB2 SILABS_DBUS_TIMER2_CC0(0x1, 0x2)
1413
#define TIMER2_CC0_PB3 SILABS_DBUS_TIMER2_CC0(0x1, 0x3)
1414
#define TIMER2_CC0_PB4 SILABS_DBUS_TIMER2_CC0(0x1, 0x4)
1415
#define TIMER2_CC1_PA0 SILABS_DBUS_TIMER2_CC1(0x0, 0x0)
1416
#define TIMER2_CC1_PA1 SILABS_DBUS_TIMER2_CC1(0x0, 0x1)
1417
#define TIMER2_CC1_PA2 SILABS_DBUS_TIMER2_CC1(0x0, 0x2)
1418
#define TIMER2_CC1_PA3 SILABS_DBUS_TIMER2_CC1(0x0, 0x3)
1419
#define TIMER2_CC1_PA4 SILABS_DBUS_TIMER2_CC1(0x0, 0x4)
1420
#define TIMER2_CC1_PA5 SILABS_DBUS_TIMER2_CC1(0x0, 0x5)
1421
#define TIMER2_CC1_PA6 SILABS_DBUS_TIMER2_CC1(0x0, 0x6)
1422
#define TIMER2_CC1_PA7 SILABS_DBUS_TIMER2_CC1(0x0, 0x7)
1423
#define TIMER2_CC1_PA8 SILABS_DBUS_TIMER2_CC1(0x0, 0x8)
1424
#define TIMER2_CC1_PB0 SILABS_DBUS_TIMER2_CC1(0x1, 0x0)
1425
#define TIMER2_CC1_PB1 SILABS_DBUS_TIMER2_CC1(0x1, 0x1)
1426
#define TIMER2_CC1_PB2 SILABS_DBUS_TIMER2_CC1(0x1, 0x2)
1427
#define TIMER2_CC1_PB3 SILABS_DBUS_TIMER2_CC1(0x1, 0x3)
1428
#define TIMER2_CC1_PB4 SILABS_DBUS_TIMER2_CC1(0x1, 0x4)
1429
#define TIMER2_CC2_PA0 SILABS_DBUS_TIMER2_CC2(0x0, 0x0)
1430
#define TIMER2_CC2_PA1 SILABS_DBUS_TIMER2_CC2(0x0, 0x1)
1431
#define TIMER2_CC2_PA2 SILABS_DBUS_TIMER2_CC2(0x0, 0x2)
1432
#define TIMER2_CC2_PA3 SILABS_DBUS_TIMER2_CC2(0x0, 0x3)
1433
#define TIMER2_CC2_PA4 SILABS_DBUS_TIMER2_CC2(0x0, 0x4)
1434
#define TIMER2_CC2_PA5 SILABS_DBUS_TIMER2_CC2(0x0, 0x5)
1435
#define TIMER2_CC2_PA6 SILABS_DBUS_TIMER2_CC2(0x0, 0x6)
1436
#define TIMER2_CC2_PA7 SILABS_DBUS_TIMER2_CC2(0x0, 0x7)
1437
#define TIMER2_CC2_PA8 SILABS_DBUS_TIMER2_CC2(0x0, 0x8)
1438
#define TIMER2_CC2_PB0 SILABS_DBUS_TIMER2_CC2(0x1, 0x0)
1439
#define TIMER2_CC2_PB1 SILABS_DBUS_TIMER2_CC2(0x1, 0x1)
1440
#define TIMER2_CC2_PB2 SILABS_DBUS_TIMER2_CC2(0x1, 0x2)
1441
#define TIMER2_CC2_PB3 SILABS_DBUS_TIMER2_CC2(0x1, 0x3)
1442
#define TIMER2_CC2_PB4 SILABS_DBUS_TIMER2_CC2(0x1, 0x4)
1443
#define TIMER2_CDTI0_PA0 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x0)
1444
#define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1)
1445
#define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2)
1446
#define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3)
1447
#define TIMER2_CDTI0_PA4 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x4)
1448
#define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5)
1449
#define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6)
1450
#define TIMER2_CDTI0_PA7 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x7)
1451
#define TIMER2_CDTI0_PA8 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x8)
1452
#define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0)
1453
#define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1)
1454
#define TIMER2_CDTI0_PB2 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x2)
1455
#define TIMER2_CDTI0_PB3 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x3)
1456
#define TIMER2_CDTI0_PB4 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x4)
1457
#define TIMER2_CDTI1_PA0 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x0)
1458
#define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1)
1459
#define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2)
1460
#define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3)
1461
#define TIMER2_CDTI1_PA4 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x4)
1462
#define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5)
1463
#define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6)
1464
#define TIMER2_CDTI1_PA7 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x7)
1465
#define TIMER2_CDTI1_PA8 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x8)
1466
#define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0)
1467
#define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1)
1468
#define TIMER2_CDTI1_PB2 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x2)
1469
#define TIMER2_CDTI1_PB3 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x3)
1470
#define TIMER2_CDTI1_PB4 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x4)
1471
#define TIMER2_CDTI2_PA0 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x0)
1472
#define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1)
1473
#define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2)
1474
#define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3)
1475
#define TIMER2_CDTI2_PA4 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x4)
1476
#define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5)
1477
#define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6)
1478
#define TIMER2_CDTI2_PA7 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x7)
1479
#define TIMER2_CDTI2_PA8 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x8)
1480
#define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0)
1481
#define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1)
1482
#define TIMER2_CDTI2_PB2 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x2)
1483
#define TIMER2_CDTI2_PB3 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x3)
1484
#define TIMER2_CDTI2_PB4 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x4)
1485
1486
#define TIMER3_CC0_PC0 SILABS_DBUS_TIMER3_CC0(0x2, 0x0)
1487
#define TIMER3_CC0_PC1 SILABS_DBUS_TIMER3_CC0(0x2, 0x1)
1488
#define TIMER3_CC0_PC2 SILABS_DBUS_TIMER3_CC0(0x2, 0x2)
1489
#define TIMER3_CC0_PC3 SILABS_DBUS_TIMER3_CC0(0x2, 0x3)
1490
#define TIMER3_CC0_PC4 SILABS_DBUS_TIMER3_CC0(0x2, 0x4)
1491
#define TIMER3_CC0_PC5 SILABS_DBUS_TIMER3_CC0(0x2, 0x5)
1492
#define TIMER3_CC0_PC6 SILABS_DBUS_TIMER3_CC0(0x2, 0x6)
1493
#define TIMER3_CC0_PC7 SILABS_DBUS_TIMER3_CC0(0x2, 0x7)
1494
#define TIMER3_CC0_PD0 SILABS_DBUS_TIMER3_CC0(0x3, 0x0)
1495
#define TIMER3_CC0_PD1 SILABS_DBUS_TIMER3_CC0(0x3, 0x1)
1496
#define TIMER3_CC0_PD2 SILABS_DBUS_TIMER3_CC0(0x3, 0x2)
1497
#define TIMER3_CC0_PD3 SILABS_DBUS_TIMER3_CC0(0x3, 0x3)
1498
#define TIMER3_CC1_PC0 SILABS_DBUS_TIMER3_CC1(0x2, 0x0)
1499
#define TIMER3_CC1_PC1 SILABS_DBUS_TIMER3_CC1(0x2, 0x1)
1500
#define TIMER3_CC1_PC2 SILABS_DBUS_TIMER3_CC1(0x2, 0x2)
1501
#define TIMER3_CC1_PC3 SILABS_DBUS_TIMER3_CC1(0x2, 0x3)
1502
#define TIMER3_CC1_PC4 SILABS_DBUS_TIMER3_CC1(0x2, 0x4)
1503
#define TIMER3_CC1_PC5 SILABS_DBUS_TIMER3_CC1(0x2, 0x5)
1504
#define TIMER3_CC1_PC6 SILABS_DBUS_TIMER3_CC1(0x2, 0x6)
1505
#define TIMER3_CC1_PC7 SILABS_DBUS_TIMER3_CC1(0x2, 0x7)
1506
#define TIMER3_CC1_PD0 SILABS_DBUS_TIMER3_CC1(0x3, 0x0)
1507
#define TIMER3_CC1_PD1 SILABS_DBUS_TIMER3_CC1(0x3, 0x1)
1508
#define TIMER3_CC1_PD2 SILABS_DBUS_TIMER3_CC1(0x3, 0x2)
1509
#define TIMER3_CC1_PD3 SILABS_DBUS_TIMER3_CC1(0x3, 0x3)
1510
#define TIMER3_CC2_PC0 SILABS_DBUS_TIMER3_CC2(0x2, 0x0)
1511
#define TIMER3_CC2_PC1 SILABS_DBUS_TIMER3_CC2(0x2, 0x1)
1512
#define TIMER3_CC2_PC2 SILABS_DBUS_TIMER3_CC2(0x2, 0x2)
1513
#define TIMER3_CC2_PC3 SILABS_DBUS_TIMER3_CC2(0x2, 0x3)
1514
#define TIMER3_CC2_PC4 SILABS_DBUS_TIMER3_CC2(0x2, 0x4)
1515
#define TIMER3_CC2_PC5 SILABS_DBUS_TIMER3_CC2(0x2, 0x5)
1516
#define TIMER3_CC2_PC6 SILABS_DBUS_TIMER3_CC2(0x2, 0x6)
1517
#define TIMER3_CC2_PC7 SILABS_DBUS_TIMER3_CC2(0x2, 0x7)
1518
#define TIMER3_CC2_PD0 SILABS_DBUS_TIMER3_CC2(0x3, 0x0)
1519
#define TIMER3_CC2_PD1 SILABS_DBUS_TIMER3_CC2(0x3, 0x1)
1520
#define TIMER3_CC2_PD2 SILABS_DBUS_TIMER3_CC2(0x3, 0x2)
1521
#define TIMER3_CC2_PD3 SILABS_DBUS_TIMER3_CC2(0x3, 0x3)
1522
#define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0)
1523
#define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1)
1524
#define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2)
1525
#define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3)
1526
#define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4)
1527
#define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5)
1528
#define TIMER3_CDTI0_PC6 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x6)
1529
#define TIMER3_CDTI0_PC7 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x7)
1530
#define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0)
1531
#define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1)
1532
#define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2)
1533
#define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3)
1534
#define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0)
1535
#define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1)
1536
#define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2)
1537
#define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3)
1538
#define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4)
1539
#define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5)
1540
#define TIMER3_CDTI1_PC6 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x6)
1541
#define TIMER3_CDTI1_PC7 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x7)
1542
#define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0)
1543
#define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1)
1544
#define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2)
1545
#define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3)
1546
#define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0)
1547
#define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1)
1548
#define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2)
1549
#define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3)
1550
#define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4)
1551
#define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5)
1552
#define TIMER3_CDTI2_PC6 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x6)
1553
#define TIMER3_CDTI2_PC7 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x7)
1554
#define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0)
1555
#define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1)
1556
#define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2)
1557
#define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3)
1558
1559
#define TIMER4_CC0_PA0 SILABS_DBUS_TIMER4_CC0(0x0, 0x0)
1560
#define TIMER4_CC0_PA1 SILABS_DBUS_TIMER4_CC0(0x0, 0x1)
1561
#define TIMER4_CC0_PA2 SILABS_DBUS_TIMER4_CC0(0x0, 0x2)
1562
#define TIMER4_CC0_PA3 SILABS_DBUS_TIMER4_CC0(0x0, 0x3)
1563
#define TIMER4_CC0_PA4 SILABS_DBUS_TIMER4_CC0(0x0, 0x4)
1564
#define TIMER4_CC0_PA5 SILABS_DBUS_TIMER4_CC0(0x0, 0x5)
1565
#define TIMER4_CC0_PA6 SILABS_DBUS_TIMER4_CC0(0x0, 0x6)
1566
#define TIMER4_CC0_PA7 SILABS_DBUS_TIMER4_CC0(0x0, 0x7)
1567
#define TIMER4_CC0_PA8 SILABS_DBUS_TIMER4_CC0(0x0, 0x8)
1568
#define TIMER4_CC0_PB0 SILABS_DBUS_TIMER4_CC0(0x1, 0x0)
1569
#define TIMER4_CC0_PB1 SILABS_DBUS_TIMER4_CC0(0x1, 0x1)
1570
#define TIMER4_CC0_PB2 SILABS_DBUS_TIMER4_CC0(0x1, 0x2)
1571
#define TIMER4_CC0_PB3 SILABS_DBUS_TIMER4_CC0(0x1, 0x3)
1572
#define TIMER4_CC0_PB4 SILABS_DBUS_TIMER4_CC0(0x1, 0x4)
1573
#define TIMER4_CC1_PA0 SILABS_DBUS_TIMER4_CC1(0x0, 0x0)
1574
#define TIMER4_CC1_PA1 SILABS_DBUS_TIMER4_CC1(0x0, 0x1)
1575
#define TIMER4_CC1_PA2 SILABS_DBUS_TIMER4_CC1(0x0, 0x2)
1576
#define TIMER4_CC1_PA3 SILABS_DBUS_TIMER4_CC1(0x0, 0x3)
1577
#define TIMER4_CC1_PA4 SILABS_DBUS_TIMER4_CC1(0x0, 0x4)
1578
#define TIMER4_CC1_PA5 SILABS_DBUS_TIMER4_CC1(0x0, 0x5)
1579
#define TIMER4_CC1_PA6 SILABS_DBUS_TIMER4_CC1(0x0, 0x6)
1580
#define TIMER4_CC1_PA7 SILABS_DBUS_TIMER4_CC1(0x0, 0x7)
1581
#define TIMER4_CC1_PA8 SILABS_DBUS_TIMER4_CC1(0x0, 0x8)
1582
#define TIMER4_CC1_PB0 SILABS_DBUS_TIMER4_CC1(0x1, 0x0)
1583
#define TIMER4_CC1_PB1 SILABS_DBUS_TIMER4_CC1(0x1, 0x1)
1584
#define TIMER4_CC1_PB2 SILABS_DBUS_TIMER4_CC1(0x1, 0x2)
1585
#define TIMER4_CC1_PB3 SILABS_DBUS_TIMER4_CC1(0x1, 0x3)
1586
#define TIMER4_CC1_PB4 SILABS_DBUS_TIMER4_CC1(0x1, 0x4)
1587
#define TIMER4_CC2_PA0 SILABS_DBUS_TIMER4_CC2(0x0, 0x0)
1588
#define TIMER4_CC2_PA1 SILABS_DBUS_TIMER4_CC2(0x0, 0x1)
1589
#define TIMER4_CC2_PA2 SILABS_DBUS_TIMER4_CC2(0x0, 0x2)
1590
#define TIMER4_CC2_PA3 SILABS_DBUS_TIMER4_CC2(0x0, 0x3)
1591
#define TIMER4_CC2_PA4 SILABS_DBUS_TIMER4_CC2(0x0, 0x4)
1592
#define TIMER4_CC2_PA5 SILABS_DBUS_TIMER4_CC2(0x0, 0x5)
1593
#define TIMER4_CC2_PA6 SILABS_DBUS_TIMER4_CC2(0x0, 0x6)
1594
#define TIMER4_CC2_PA7 SILABS_DBUS_TIMER4_CC2(0x0, 0x7)
1595
#define TIMER4_CC2_PA8 SILABS_DBUS_TIMER4_CC2(0x0, 0x8)
1596
#define TIMER4_CC2_PB0 SILABS_DBUS_TIMER4_CC2(0x1, 0x0)
1597
#define TIMER4_CC2_PB1 SILABS_DBUS_TIMER4_CC2(0x1, 0x1)
1598
#define TIMER4_CC2_PB2 SILABS_DBUS_TIMER4_CC2(0x1, 0x2)
1599
#define TIMER4_CC2_PB3 SILABS_DBUS_TIMER4_CC2(0x1, 0x3)
1600
#define TIMER4_CC2_PB4 SILABS_DBUS_TIMER4_CC2(0x1, 0x4)
1601
#define TIMER4_CDTI0_PA0 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x0)
1602
#define TIMER4_CDTI0_PA1 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x1)
1603
#define TIMER4_CDTI0_PA2 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x2)
1604
#define TIMER4_CDTI0_PA3 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x3)
1605
#define TIMER4_CDTI0_PA4 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x4)
1606
#define TIMER4_CDTI0_PA5 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x5)
1607
#define TIMER4_CDTI0_PA6 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x6)
1608
#define TIMER4_CDTI0_PA7 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x7)
1609
#define TIMER4_CDTI0_PA8 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x8)
1610
#define TIMER4_CDTI0_PB0 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x0)
1611
#define TIMER4_CDTI0_PB1 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x1)
1612
#define TIMER4_CDTI0_PB2 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x2)
1613
#define TIMER4_CDTI0_PB3 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x3)
1614
#define TIMER4_CDTI0_PB4 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x4)
1615
#define TIMER4_CDTI1_PA0 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x0)
1616
#define TIMER4_CDTI1_PA1 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x1)
1617
#define TIMER4_CDTI1_PA2 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x2)
1618
#define TIMER4_CDTI1_PA3 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x3)
1619
#define TIMER4_CDTI1_PA4 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x4)
1620
#define TIMER4_CDTI1_PA5 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x5)
1621
#define TIMER4_CDTI1_PA6 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x6)
1622
#define TIMER4_CDTI1_PA7 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x7)
1623
#define TIMER4_CDTI1_PA8 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x8)
1624
#define TIMER4_CDTI1_PB0 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x0)
1625
#define TIMER4_CDTI1_PB1 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x1)
1626
#define TIMER4_CDTI1_PB2 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x2)
1627
#define TIMER4_CDTI1_PB3 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x3)
1628
#define TIMER4_CDTI1_PB4 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x4)
1629
#define TIMER4_CDTI2_PA0 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x0)
1630
#define TIMER4_CDTI2_PA1 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x1)
1631
#define TIMER4_CDTI2_PA2 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x2)
1632
#define TIMER4_CDTI2_PA3 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x3)
1633
#define TIMER4_CDTI2_PA4 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x4)
1634
#define TIMER4_CDTI2_PA5 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x5)
1635
#define TIMER4_CDTI2_PA6 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x6)
1636
#define TIMER4_CDTI2_PA7 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x7)
1637
#define TIMER4_CDTI2_PA8 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x8)
1638
#define TIMER4_CDTI2_PB0 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x0)
1639
#define TIMER4_CDTI2_PB1 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x1)
1640
#define TIMER4_CDTI2_PB2 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x2)
1641
#define TIMER4_CDTI2_PB3 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x3)
1642
#define TIMER4_CDTI2_PB4 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x4)
1643
1644
#define USART0_CS_PA0 SILABS_DBUS_USART0_CS(0x0, 0x0)
1645
#define USART0_CS_PA1 SILABS_DBUS_USART0_CS(0x0, 0x1)
1646
#define USART0_CS_PA2 SILABS_DBUS_USART0_CS(0x0, 0x2)
1647
#define USART0_CS_PA3 SILABS_DBUS_USART0_CS(0x0, 0x3)
1648
#define USART0_CS_PA4 SILABS_DBUS_USART0_CS(0x0, 0x4)
1649
#define USART0_CS_PA5 SILABS_DBUS_USART0_CS(0x0, 0x5)
1650
#define USART0_CS_PA6 SILABS_DBUS_USART0_CS(0x0, 0x6)
1651
#define USART0_CS_PA7 SILABS_DBUS_USART0_CS(0x0, 0x7)
1652
#define USART0_CS_PA8 SILABS_DBUS_USART0_CS(0x0, 0x8)
1653
#define USART0_CS_PB0 SILABS_DBUS_USART0_CS(0x1, 0x0)
1654
#define USART0_CS_PB1 SILABS_DBUS_USART0_CS(0x1, 0x1)
1655
#define USART0_CS_PB2 SILABS_DBUS_USART0_CS(0x1, 0x2)
1656
#define USART0_CS_PB3 SILABS_DBUS_USART0_CS(0x1, 0x3)
1657
#define USART0_CS_PB4 SILABS_DBUS_USART0_CS(0x1, 0x4)
1658
#define USART0_CS_PC0 SILABS_DBUS_USART0_CS(0x2, 0x0)
1659
#define USART0_CS_PC1 SILABS_DBUS_USART0_CS(0x2, 0x1)
1660
#define USART0_CS_PC2 SILABS_DBUS_USART0_CS(0x2, 0x2)
1661
#define USART0_CS_PC3 SILABS_DBUS_USART0_CS(0x2, 0x3)
1662
#define USART0_CS_PC4 SILABS_DBUS_USART0_CS(0x2, 0x4)
1663
#define USART0_CS_PC5 SILABS_DBUS_USART0_CS(0x2, 0x5)
1664
#define USART0_CS_PC6 SILABS_DBUS_USART0_CS(0x2, 0x6)
1665
#define USART0_CS_PC7 SILABS_DBUS_USART0_CS(0x2, 0x7)
1666
#define USART0_CS_PD0 SILABS_DBUS_USART0_CS(0x3, 0x0)
1667
#define USART0_CS_PD1 SILABS_DBUS_USART0_CS(0x3, 0x1)
1668
#define USART0_CS_PD2 SILABS_DBUS_USART0_CS(0x3, 0x2)
1669
#define USART0_CS_PD3 SILABS_DBUS_USART0_CS(0x3, 0x3)
1670
#define USART0_RTS_PA0 SILABS_DBUS_USART0_RTS(0x0, 0x0)
1671
#define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1)
1672
#define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2)
1673
#define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3)
1674
#define USART0_RTS_PA4 SILABS_DBUS_USART0_RTS(0x0, 0x4)
1675
#define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5)
1676
#define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6)
1677
#define USART0_RTS_PA7 SILABS_DBUS_USART0_RTS(0x0, 0x7)
1678
#define USART0_RTS_PA8 SILABS_DBUS_USART0_RTS(0x0, 0x8)
1679
#define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0)
1680
#define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1)
1681
#define USART0_RTS_PB2 SILABS_DBUS_USART0_RTS(0x1, 0x2)
1682
#define USART0_RTS_PB3 SILABS_DBUS_USART0_RTS(0x1, 0x3)
1683
#define USART0_RTS_PB4 SILABS_DBUS_USART0_RTS(0x1, 0x4)
1684
#define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0)
1685
#define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1)
1686
#define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2)
1687
#define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3)
1688
#define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4)
1689
#define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5)
1690
#define USART0_RTS_PC6 SILABS_DBUS_USART0_RTS(0x2, 0x6)
1691
#define USART0_RTS_PC7 SILABS_DBUS_USART0_RTS(0x2, 0x7)
1692
#define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0)
1693
#define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1)
1694
#define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2)
1695
#define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3)
1696
#define USART0_RX_PA0 SILABS_DBUS_USART0_RX(0x0, 0x0)
1697
#define USART0_RX_PA1 SILABS_DBUS_USART0_RX(0x0, 0x1)
1698
#define USART0_RX_PA2 SILABS_DBUS_USART0_RX(0x0, 0x2)
1699
#define USART0_RX_PA3 SILABS_DBUS_USART0_RX(0x0, 0x3)
1700
#define USART0_RX_PA4 SILABS_DBUS_USART0_RX(0x0, 0x4)
1701
#define USART0_RX_PA5 SILABS_DBUS_USART0_RX(0x0, 0x5)
1702
#define USART0_RX_PA6 SILABS_DBUS_USART0_RX(0x0, 0x6)
1703
#define USART0_RX_PA7 SILABS_DBUS_USART0_RX(0x0, 0x7)
1704
#define USART0_RX_PA8 SILABS_DBUS_USART0_RX(0x0, 0x8)
1705
#define USART0_RX_PB0 SILABS_DBUS_USART0_RX(0x1, 0x0)
1706
#define USART0_RX_PB1 SILABS_DBUS_USART0_RX(0x1, 0x1)
1707
#define USART0_RX_PB2 SILABS_DBUS_USART0_RX(0x1, 0x2)
1708
#define USART0_RX_PB3 SILABS_DBUS_USART0_RX(0x1, 0x3)
1709
#define USART0_RX_PB4 SILABS_DBUS_USART0_RX(0x1, 0x4)
1710
#define USART0_RX_PC0 SILABS_DBUS_USART0_RX(0x2, 0x0)
1711
#define USART0_RX_PC1 SILABS_DBUS_USART0_RX(0x2, 0x1)
1712
#define USART0_RX_PC2 SILABS_DBUS_USART0_RX(0x2, 0x2)
1713
#define USART0_RX_PC3 SILABS_DBUS_USART0_RX(0x2, 0x3)
1714
#define USART0_RX_PC4 SILABS_DBUS_USART0_RX(0x2, 0x4)
1715
#define USART0_RX_PC5 SILABS_DBUS_USART0_RX(0x2, 0x5)
1716
#define USART0_RX_PC6 SILABS_DBUS_USART0_RX(0x2, 0x6)
1717
#define USART0_RX_PC7 SILABS_DBUS_USART0_RX(0x2, 0x7)
1718
#define USART0_RX_PD0 SILABS_DBUS_USART0_RX(0x3, 0x0)
1719
#define USART0_RX_PD1 SILABS_DBUS_USART0_RX(0x3, 0x1)
1720
#define USART0_RX_PD2 SILABS_DBUS_USART0_RX(0x3, 0x2)
1721
#define USART0_RX_PD3 SILABS_DBUS_USART0_RX(0x3, 0x3)
1722
#define USART0_CLK_PA0 SILABS_DBUS_USART0_CLK(0x0, 0x0)
1723
#define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1)
1724
#define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2)
1725
#define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3)
1726
#define USART0_CLK_PA4 SILABS_DBUS_USART0_CLK(0x0, 0x4)
1727
#define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5)
1728
#define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6)
1729
#define USART0_CLK_PA7 SILABS_DBUS_USART0_CLK(0x0, 0x7)
1730
#define USART0_CLK_PA8 SILABS_DBUS_USART0_CLK(0x0, 0x8)
1731
#define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0)
1732
#define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1)
1733
#define USART0_CLK_PB2 SILABS_DBUS_USART0_CLK(0x1, 0x2)
1734
#define USART0_CLK_PB3 SILABS_DBUS_USART0_CLK(0x1, 0x3)
1735
#define USART0_CLK_PB4 SILABS_DBUS_USART0_CLK(0x1, 0x4)
1736
#define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0)
1737
#define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1)
1738
#define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2)
1739
#define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3)
1740
#define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4)
1741
#define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5)
1742
#define USART0_CLK_PC6 SILABS_DBUS_USART0_CLK(0x2, 0x6)
1743
#define USART0_CLK_PC7 SILABS_DBUS_USART0_CLK(0x2, 0x7)
1744
#define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0)
1745
#define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1)
1746
#define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2)
1747
#define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3)
1748
#define USART0_TX_PA0 SILABS_DBUS_USART0_TX(0x0, 0x0)
1749
#define USART0_TX_PA1 SILABS_DBUS_USART0_TX(0x0, 0x1)
1750
#define USART0_TX_PA2 SILABS_DBUS_USART0_TX(0x0, 0x2)
1751
#define USART0_TX_PA3 SILABS_DBUS_USART0_TX(0x0, 0x3)
1752
#define USART0_TX_PA4 SILABS_DBUS_USART0_TX(0x0, 0x4)
1753
#define USART0_TX_PA5 SILABS_DBUS_USART0_TX(0x0, 0x5)
1754
#define USART0_TX_PA6 SILABS_DBUS_USART0_TX(0x0, 0x6)
1755
#define USART0_TX_PA7 SILABS_DBUS_USART0_TX(0x0, 0x7)
1756
#define USART0_TX_PA8 SILABS_DBUS_USART0_TX(0x0, 0x8)
1757
#define USART0_TX_PB0 SILABS_DBUS_USART0_TX(0x1, 0x0)
1758
#define USART0_TX_PB1 SILABS_DBUS_USART0_TX(0x1, 0x1)
1759
#define USART0_TX_PB2 SILABS_DBUS_USART0_TX(0x1, 0x2)
1760
#define USART0_TX_PB3 SILABS_DBUS_USART0_TX(0x1, 0x3)
1761
#define USART0_TX_PB4 SILABS_DBUS_USART0_TX(0x1, 0x4)
1762
#define USART0_TX_PC0 SILABS_DBUS_USART0_TX(0x2, 0x0)
1763
#define USART0_TX_PC1 SILABS_DBUS_USART0_TX(0x2, 0x1)
1764
#define USART0_TX_PC2 SILABS_DBUS_USART0_TX(0x2, 0x2)
1765
#define USART0_TX_PC3 SILABS_DBUS_USART0_TX(0x2, 0x3)
1766
#define USART0_TX_PC4 SILABS_DBUS_USART0_TX(0x2, 0x4)
1767
#define USART0_TX_PC5 SILABS_DBUS_USART0_TX(0x2, 0x5)
1768
#define USART0_TX_PC6 SILABS_DBUS_USART0_TX(0x2, 0x6)
1769
#define USART0_TX_PC7 SILABS_DBUS_USART0_TX(0x2, 0x7)
1770
#define USART0_TX_PD0 SILABS_DBUS_USART0_TX(0x3, 0x0)
1771
#define USART0_TX_PD1 SILABS_DBUS_USART0_TX(0x3, 0x1)
1772
#define USART0_TX_PD2 SILABS_DBUS_USART0_TX(0x3, 0x2)
1773
#define USART0_TX_PD3 SILABS_DBUS_USART0_TX(0x3, 0x3)
1774
#define USART0_CTS_PA0 SILABS_DBUS_USART0_CTS(0x0, 0x0)
1775
#define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1)
1776
#define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2)
1777
#define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3)
1778
#define USART0_CTS_PA4 SILABS_DBUS_USART0_CTS(0x0, 0x4)
1779
#define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5)
1780
#define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6)
1781
#define USART0_CTS_PA7 SILABS_DBUS_USART0_CTS(0x0, 0x7)
1782
#define USART0_CTS_PA8 SILABS_DBUS_USART0_CTS(0x0, 0x8)
1783
#define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0)
1784
#define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1)
1785
#define USART0_CTS_PB2 SILABS_DBUS_USART0_CTS(0x1, 0x2)
1786
#define USART0_CTS_PB3 SILABS_DBUS_USART0_CTS(0x1, 0x3)
1787
#define USART0_CTS_PB4 SILABS_DBUS_USART0_CTS(0x1, 0x4)
1788
#define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0)
1789
#define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1)
1790
#define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2)
1791
#define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3)
1792
#define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4)
1793
#define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5)
1794
#define USART0_CTS_PC6 SILABS_DBUS_USART0_CTS(0x2, 0x6)
1795
#define USART0_CTS_PC7 SILABS_DBUS_USART0_CTS(0x2, 0x7)
1796
#define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0)
1797
#define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1)
1798
#define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2)
1799
#define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3)
1800
1801
#define USART1_CS_PA0 SILABS_DBUS_USART1_CS(0x0, 0x0)
1802
#define USART1_CS_PA1 SILABS_DBUS_USART1_CS(0x0, 0x1)
1803
#define USART1_CS_PA2 SILABS_DBUS_USART1_CS(0x0, 0x2)
1804
#define USART1_CS_PA3 SILABS_DBUS_USART1_CS(0x0, 0x3)
1805
#define USART1_CS_PA4 SILABS_DBUS_USART1_CS(0x0, 0x4)
1806
#define USART1_CS_PA5 SILABS_DBUS_USART1_CS(0x0, 0x5)
1807
#define USART1_CS_PA6 SILABS_DBUS_USART1_CS(0x0, 0x6)
1808
#define USART1_CS_PA7 SILABS_DBUS_USART1_CS(0x0, 0x7)
1809
#define USART1_CS_PA8 SILABS_DBUS_USART1_CS(0x0, 0x8)
1810
#define USART1_CS_PB0 SILABS_DBUS_USART1_CS(0x1, 0x0)
1811
#define USART1_CS_PB1 SILABS_DBUS_USART1_CS(0x1, 0x1)
1812
#define USART1_CS_PB2 SILABS_DBUS_USART1_CS(0x1, 0x2)
1813
#define USART1_CS_PB3 SILABS_DBUS_USART1_CS(0x1, 0x3)
1814
#define USART1_CS_PB4 SILABS_DBUS_USART1_CS(0x1, 0x4)
1815
#define USART1_RTS_PA0 SILABS_DBUS_USART1_RTS(0x0, 0x0)
1816
#define USART1_RTS_PA1 SILABS_DBUS_USART1_RTS(0x0, 0x1)
1817
#define USART1_RTS_PA2 SILABS_DBUS_USART1_RTS(0x0, 0x2)
1818
#define USART1_RTS_PA3 SILABS_DBUS_USART1_RTS(0x0, 0x3)
1819
#define USART1_RTS_PA4 SILABS_DBUS_USART1_RTS(0x0, 0x4)
1820
#define USART1_RTS_PA5 SILABS_DBUS_USART1_RTS(0x0, 0x5)
1821
#define USART1_RTS_PA6 SILABS_DBUS_USART1_RTS(0x0, 0x6)
1822
#define USART1_RTS_PA7 SILABS_DBUS_USART1_RTS(0x0, 0x7)
1823
#define USART1_RTS_PA8 SILABS_DBUS_USART1_RTS(0x0, 0x8)
1824
#define USART1_RTS_PB0 SILABS_DBUS_USART1_RTS(0x1, 0x0)
1825
#define USART1_RTS_PB1 SILABS_DBUS_USART1_RTS(0x1, 0x1)
1826
#define USART1_RTS_PB2 SILABS_DBUS_USART1_RTS(0x1, 0x2)
1827
#define USART1_RTS_PB3 SILABS_DBUS_USART1_RTS(0x1, 0x3)
1828
#define USART1_RTS_PB4 SILABS_DBUS_USART1_RTS(0x1, 0x4)
1829
#define USART1_RX_PA0 SILABS_DBUS_USART1_RX(0x0, 0x0)
1830
#define USART1_RX_PA1 SILABS_DBUS_USART1_RX(0x0, 0x1)
1831
#define USART1_RX_PA2 SILABS_DBUS_USART1_RX(0x0, 0x2)
1832
#define USART1_RX_PA3 SILABS_DBUS_USART1_RX(0x0, 0x3)
1833
#define USART1_RX_PA4 SILABS_DBUS_USART1_RX(0x0, 0x4)
1834
#define USART1_RX_PA5 SILABS_DBUS_USART1_RX(0x0, 0x5)
1835
#define USART1_RX_PA6 SILABS_DBUS_USART1_RX(0x0, 0x6)
1836
#define USART1_RX_PA7 SILABS_DBUS_USART1_RX(0x0, 0x7)
1837
#define USART1_RX_PA8 SILABS_DBUS_USART1_RX(0x0, 0x8)
1838
#define USART1_RX_PB0 SILABS_DBUS_USART1_RX(0x1, 0x0)
1839
#define USART1_RX_PB1 SILABS_DBUS_USART1_RX(0x1, 0x1)
1840
#define USART1_RX_PB2 SILABS_DBUS_USART1_RX(0x1, 0x2)
1841
#define USART1_RX_PB3 SILABS_DBUS_USART1_RX(0x1, 0x3)
1842
#define USART1_RX_PB4 SILABS_DBUS_USART1_RX(0x1, 0x4)
1843
#define USART1_CLK_PA0 SILABS_DBUS_USART1_CLK(0x0, 0x0)
1844
#define USART1_CLK_PA1 SILABS_DBUS_USART1_CLK(0x0, 0x1)
1845
#define USART1_CLK_PA2 SILABS_DBUS_USART1_CLK(0x0, 0x2)
1846
#define USART1_CLK_PA3 SILABS_DBUS_USART1_CLK(0x0, 0x3)
1847
#define USART1_CLK_PA4 SILABS_DBUS_USART1_CLK(0x0, 0x4)
1848
#define USART1_CLK_PA5 SILABS_DBUS_USART1_CLK(0x0, 0x5)
1849
#define USART1_CLK_PA6 SILABS_DBUS_USART1_CLK(0x0, 0x6)
1850
#define USART1_CLK_PA7 SILABS_DBUS_USART1_CLK(0x0, 0x7)
1851
#define USART1_CLK_PA8 SILABS_DBUS_USART1_CLK(0x0, 0x8)
1852
#define USART1_CLK_PB0 SILABS_DBUS_USART1_CLK(0x1, 0x0)
1853
#define USART1_CLK_PB1 SILABS_DBUS_USART1_CLK(0x1, 0x1)
1854
#define USART1_CLK_PB2 SILABS_DBUS_USART1_CLK(0x1, 0x2)
1855
#define USART1_CLK_PB3 SILABS_DBUS_USART1_CLK(0x1, 0x3)
1856
#define USART1_CLK_PB4 SILABS_DBUS_USART1_CLK(0x1, 0x4)
1857
#define USART1_TX_PA0 SILABS_DBUS_USART1_TX(0x0, 0x0)
1858
#define USART1_TX_PA1 SILABS_DBUS_USART1_TX(0x0, 0x1)
1859
#define USART1_TX_PA2 SILABS_DBUS_USART1_TX(0x0, 0x2)
1860
#define USART1_TX_PA3 SILABS_DBUS_USART1_TX(0x0, 0x3)
1861
#define USART1_TX_PA4 SILABS_DBUS_USART1_TX(0x0, 0x4)
1862
#define USART1_TX_PA5 SILABS_DBUS_USART1_TX(0x0, 0x5)
1863
#define USART1_TX_PA6 SILABS_DBUS_USART1_TX(0x0, 0x6)
1864
#define USART1_TX_PA7 SILABS_DBUS_USART1_TX(0x0, 0x7)
1865
#define USART1_TX_PA8 SILABS_DBUS_USART1_TX(0x0, 0x8)
1866
#define USART1_TX_PB0 SILABS_DBUS_USART1_TX(0x1, 0x0)
1867
#define USART1_TX_PB1 SILABS_DBUS_USART1_TX(0x1, 0x1)
1868
#define USART1_TX_PB2 SILABS_DBUS_USART1_TX(0x1, 0x2)
1869
#define USART1_TX_PB3 SILABS_DBUS_USART1_TX(0x1, 0x3)
1870
#define USART1_TX_PB4 SILABS_DBUS_USART1_TX(0x1, 0x4)
1871
#define USART1_CTS_PA0 SILABS_DBUS_USART1_CTS(0x0, 0x0)
1872
#define USART1_CTS_PA1 SILABS_DBUS_USART1_CTS(0x0, 0x1)
1873
#define USART1_CTS_PA2 SILABS_DBUS_USART1_CTS(0x0, 0x2)
1874
#define USART1_CTS_PA3 SILABS_DBUS_USART1_CTS(0x0, 0x3)
1875
#define USART1_CTS_PA4 SILABS_DBUS_USART1_CTS(0x0, 0x4)
1876
#define USART1_CTS_PA5 SILABS_DBUS_USART1_CTS(0x0, 0x5)
1877
#define USART1_CTS_PA6 SILABS_DBUS_USART1_CTS(0x0, 0x6)
1878
#define USART1_CTS_PA7 SILABS_DBUS_USART1_CTS(0x0, 0x7)
1879
#define USART1_CTS_PA8 SILABS_DBUS_USART1_CTS(0x0, 0x8)
1880
#define USART1_CTS_PB0 SILABS_DBUS_USART1_CTS(0x1, 0x0)
1881
#define USART1_CTS_PB1 SILABS_DBUS_USART1_CTS(0x1, 0x1)
1882
#define USART1_CTS_PB2 SILABS_DBUS_USART1_CTS(0x1, 0x2)
1883
#define USART1_CTS_PB3 SILABS_DBUS_USART1_CTS(0x1, 0x3)
1884
#define USART1_CTS_PB4 SILABS_DBUS_USART1_CTS(0x1, 0x4)
1885
1886
#define ABUS_AEVEN0_IADC0 SILABS_ABUS(0x0, 0x0, 0x1)
1887
#define ABUS_AEVEN0_ACMP0 SILABS_ABUS(0x0, 0x0, 0x2)
1888
#define ABUS_AEVEN1_IADC0 SILABS_ABUS(0x0, 0x1, 0x1)
1889
#define ABUS_AEVEN1_ACMP0 SILABS_ABUS(0x0, 0x1, 0x2)
1890
#define ABUS_AODD0_IADC0 SILABS_ABUS(0x0, 0x2, 0x1)
1891
#define ABUS_AODD0_ACMP0 SILABS_ABUS(0x0, 0x2, 0x2)
1892
#define ABUS_AODD1_IADC0 SILABS_ABUS(0x0, 0x3, 0x1)
1893
#define ABUS_AODD1_ACMP0 SILABS_ABUS(0x0, 0x3, 0x2)
1894
#define ABUS_BEVEN0_IADC0 SILABS_ABUS(0x1, 0x0, 0x1)
1895
#define ABUS_BEVEN0_ACMP0 SILABS_ABUS(0x1, 0x0, 0x2)
1896
#define ABUS_BEVEN1_IADC0 SILABS_ABUS(0x1, 0x1, 0x1)
1897
#define ABUS_BEVEN1_ACMP0 SILABS_ABUS(0x1, 0x1, 0x2)
1898
#define ABUS_BODD0_IADC0 SILABS_ABUS(0x1, 0x2, 0x1)
1899
#define ABUS_BODD0_ACMP0 SILABS_ABUS(0x1, 0x2, 0x2)
1900
#define ABUS_BODD1_IADC0 SILABS_ABUS(0x1, 0x3, 0x1)
1901
#define ABUS_BODD1_ACMP0 SILABS_ABUS(0x1, 0x3, 0x2)
1902
#define ABUS_CDEVEN0_IADC0 SILABS_ABUS(0x2, 0x0, 0x1)
1903
#define ABUS_CDEVEN0_ACMP0 SILABS_ABUS(0x2, 0x0, 0x2)
1904
#define ABUS_CDEVEN1_IADC0 SILABS_ABUS(0x2, 0x1, 0x1)
1905
#define ABUS_CDEVEN1_ACMP0 SILABS_ABUS(0x2, 0x1, 0x2)
1906
#define ABUS_CDODD0_IADC0 SILABS_ABUS(0x2, 0x2, 0x1)
1907
#define ABUS_CDODD0_ACMP0 SILABS_ABUS(0x2, 0x2, 0x2)
1908
#define ABUS_CDODD0_PMON SILABS_ABUS(0x2, 0x2, 0xc)
1909
#define ABUS_CDODD1_IADC0 SILABS_ABUS(0x2, 0x3, 0x1)
1910
#define ABUS_CDODD1_ACMP0 SILABS_ABUS(0x2, 0x3, 0x2)
1911
1912
#endif
/* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG27_PINCTRL_H_ */
silabs-pinctrl-dbus.h
include
zephyr
dt-bindings
pinctrl
silabs
xg27-pinctrl.h
Generated on Sun May 4 2025 13:59:46 for Zephyr Project API by
1.9.8
1.9.8