Zephyr Project API
4.1.99
A Scalable Open Source RTOS
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xg29-pinctrl.h
Go to the documentation of this file.
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/*
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* Copyright (c) 2025 Silicon Laboratories Inc.
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* SPDX-License-Identifier: Apache-2.0
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*
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* Pin Control for Silicon Labs XG29 devices
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*
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* This file was generated by the script gen_pinctrl.py in the hal_silabs module.
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* Do not manually edit.
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*/
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#ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG29_PINCTRL_H_
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#define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG29_PINCTRL_H_
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#include <
dt-bindings/pinctrl/silabs-pinctrl-dbus.h
>
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#define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
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#define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 2)
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#define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 7, 1, 1, 3)
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#define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 7, 1, 2, 4)
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#define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 7, 0, 0, 1)
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#define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1)
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#define SILABS_DBUS_EUSART0_RTS(port, pin) SILABS_DBUS(port, pin, 19, 1, 1, 3)
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#define SILABS_DBUS_EUSART0_RX(port, pin) SILABS_DBUS(port, pin, 19, 1, 2, 4)
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#define SILABS_DBUS_EUSART0_SCLK(port, pin) SILABS_DBUS(port, pin, 19, 1, 3, 5)
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#define SILABS_DBUS_EUSART0_TX(port, pin) SILABS_DBUS(port, pin, 19, 1, 4, 6)
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#define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 19, 0, 0, 2)
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#define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 27, 1, 0, 1)
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#define SILABS_DBUS_EUSART1_RTS(port, pin) SILABS_DBUS(port, pin, 27, 1, 1, 3)
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#define SILABS_DBUS_EUSART1_RX(port, pin) SILABS_DBUS(port, pin, 27, 1, 2, 4)
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#define SILABS_DBUS_EUSART1_SCLK(port, pin) SILABS_DBUS(port, pin, 27, 1, 3, 5)
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#define SILABS_DBUS_EUSART1_TX(port, pin) SILABS_DBUS(port, pin, 27, 1, 4, 6)
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#define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 27, 0, 0, 2)
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#define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 35, 1, 0, 1)
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#define SILABS_DBUS_PTI_DFRAME(port, pin) SILABS_DBUS(port, pin, 35, 1, 1, 2)
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#define SILABS_DBUS_PTI_DOUT(port, pin) SILABS_DBUS(port, pin, 35, 1, 2, 3)
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#define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 40, 1, 0, 1)
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#define SILABS_DBUS_I2C0_SDA(port, pin) SILABS_DBUS(port, pin, 40, 1, 1, 2)
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#define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 44, 1, 0, 1)
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#define SILABS_DBUS_I2C1_SDA(port, pin) SILABS_DBUS(port, pin, 44, 1, 1, 2)
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#define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 48, 1, 0, 1)
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#define SILABS_DBUS_LETIMER0_OUT1(port, pin) SILABS_DBUS(port, pin, 48, 1, 1, 2)
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#define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 52, 1, 0, 1)
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#define SILABS_DBUS_MODEM_ANT1(port, pin) SILABS_DBUS(port, pin, 52, 1, 1, 2)
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#define SILABS_DBUS_MODEM_ANTROLLOVER(port, pin) SILABS_DBUS(port, pin, 52, 1, 2, 3)
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#define SILABS_DBUS_MODEM_ANTRR0(port, pin) SILABS_DBUS(port, pin, 52, 1, 3, 4)
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#define SILABS_DBUS_MODEM_ANTRR1(port, pin) SILABS_DBUS(port, pin, 52, 1, 4, 5)
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#define SILABS_DBUS_MODEM_ANTRR2(port, pin) SILABS_DBUS(port, pin, 52, 1, 5, 6)
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#define SILABS_DBUS_MODEM_ANTRR3(port, pin) SILABS_DBUS(port, pin, 52, 1, 6, 7)
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#define SILABS_DBUS_MODEM_ANTRR4(port, pin) SILABS_DBUS(port, pin, 52, 1, 7, 8)
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#define SILABS_DBUS_MODEM_ANTRR5(port, pin) SILABS_DBUS(port, pin, 52, 1, 8, 9)
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#define SILABS_DBUS_MODEM_ANTSWEN(port, pin) SILABS_DBUS(port, pin, 52, 1, 9, 10)
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#define SILABS_DBUS_MODEM_ANTSWUS(port, pin) SILABS_DBUS(port, pin, 52, 1, 10, 11)
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#define SILABS_DBUS_MODEM_ANTTRIG(port, pin) SILABS_DBUS(port, pin, 52, 1, 11, 12)
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#define SILABS_DBUS_MODEM_ANTTRIGSTOP(port, pin) SILABS_DBUS(port, pin, 52, 1, 12, 13)
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#define SILABS_DBUS_MODEM_DCLK(port, pin) SILABS_DBUS(port, pin, 52, 1, 13, 14)
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#define SILABS_DBUS_MODEM_DOUT(port, pin) SILABS_DBUS(port, pin, 52, 1, 14, 16)
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#define SILABS_DBUS_MODEM_DIN(port, pin) SILABS_DBUS(port, pin, 52, 0, 0, 15)
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#define SILABS_DBUS_PDM_CLK(port, pin) SILABS_DBUS(port, pin, 70, 1, 0, 1)
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#define SILABS_DBUS_PDM_DAT0(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 2)
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#define SILABS_DBUS_PDM_DAT1(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 3)
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#define SILABS_DBUS_PRS0_ASYNCH0(port, pin) SILABS_DBUS(port, pin, 75, 1, 0, 1)
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#define SILABS_DBUS_PRS0_ASYNCH1(port, pin) SILABS_DBUS(port, pin, 75, 1, 1, 2)
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#define SILABS_DBUS_PRS0_ASYNCH2(port, pin) SILABS_DBUS(port, pin, 75, 1, 2, 3)
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#define SILABS_DBUS_PRS0_ASYNCH3(port, pin) SILABS_DBUS(port, pin, 75, 1, 3, 4)
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#define SILABS_DBUS_PRS0_ASYNCH4(port, pin) SILABS_DBUS(port, pin, 75, 1, 4, 5)
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#define SILABS_DBUS_PRS0_ASYNCH5(port, pin) SILABS_DBUS(port, pin, 75, 1, 5, 6)
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#define SILABS_DBUS_PRS0_ASYNCH6(port, pin) SILABS_DBUS(port, pin, 75, 1, 6, 7)
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#define SILABS_DBUS_PRS0_ASYNCH7(port, pin) SILABS_DBUS(port, pin, 75, 1, 7, 8)
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#define SILABS_DBUS_PRS0_ASYNCH8(port, pin) SILABS_DBUS(port, pin, 75, 1, 8, 9)
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#define SILABS_DBUS_PRS0_ASYNCH9(port, pin) SILABS_DBUS(port, pin, 75, 1, 9, 10)
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#define SILABS_DBUS_PRS0_ASYNCH10(port, pin) SILABS_DBUS(port, pin, 75, 1, 10, 11)
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#define SILABS_DBUS_PRS0_ASYNCH11(port, pin) SILABS_DBUS(port, pin, 75, 1, 11, 12)
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#define SILABS_DBUS_PRS0_SYNCH0(port, pin) SILABS_DBUS(port, pin, 75, 1, 12, 13)
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#define SILABS_DBUS_PRS0_SYNCH1(port, pin) SILABS_DBUS(port, pin, 75, 1, 13, 14)
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#define SILABS_DBUS_PRS0_SYNCH2(port, pin) SILABS_DBUS(port, pin, 75, 1, 14, 15)
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#define SILABS_DBUS_PRS0_SYNCH3(port, pin) SILABS_DBUS(port, pin, 75, 1, 15, 16)
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#define SILABS_DBUS_TIMER0_CC0(port, pin) SILABS_DBUS(port, pin, 93, 1, 0, 1)
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#define SILABS_DBUS_TIMER0_CC1(port, pin) SILABS_DBUS(port, pin, 93, 1, 1, 2)
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#define SILABS_DBUS_TIMER0_CC2(port, pin) SILABS_DBUS(port, pin, 93, 1, 2, 3)
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#define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 93, 1, 3, 4)
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#define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 93, 1, 4, 5)
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#define SILABS_DBUS_TIMER0_CDTI2(port, pin) SILABS_DBUS(port, pin, 93, 1, 5, 6)
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#define SILABS_DBUS_TIMER1_CC0(port, pin) SILABS_DBUS(port, pin, 101, 1, 0, 1)
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#define SILABS_DBUS_TIMER1_CC1(port, pin) SILABS_DBUS(port, pin, 101, 1, 1, 2)
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#define SILABS_DBUS_TIMER1_CC2(port, pin) SILABS_DBUS(port, pin, 101, 1, 2, 3)
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#define SILABS_DBUS_TIMER1_CDTI0(port, pin) SILABS_DBUS(port, pin, 101, 1, 3, 4)
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#define SILABS_DBUS_TIMER1_CDTI1(port, pin) SILABS_DBUS(port, pin, 101, 1, 4, 5)
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#define SILABS_DBUS_TIMER1_CDTI2(port, pin) SILABS_DBUS(port, pin, 101, 1, 5, 6)
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#define SILABS_DBUS_TIMER2_CC0(port, pin) SILABS_DBUS(port, pin, 109, 1, 0, 1)
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#define SILABS_DBUS_TIMER2_CC1(port, pin) SILABS_DBUS(port, pin, 109, 1, 1, 2)
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#define SILABS_DBUS_TIMER2_CC2(port, pin) SILABS_DBUS(port, pin, 109, 1, 2, 3)
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#define SILABS_DBUS_TIMER2_CDTI0(port, pin) SILABS_DBUS(port, pin, 109, 1, 3, 4)
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#define SILABS_DBUS_TIMER2_CDTI1(port, pin) SILABS_DBUS(port, pin, 109, 1, 4, 5)
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#define SILABS_DBUS_TIMER2_CDTI2(port, pin) SILABS_DBUS(port, pin, 109, 1, 5, 6)
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#define SILABS_DBUS_TIMER3_CC0(port, pin) SILABS_DBUS(port, pin, 117, 1, 0, 1)
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#define SILABS_DBUS_TIMER3_CC1(port, pin) SILABS_DBUS(port, pin, 117, 1, 1, 2)
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#define SILABS_DBUS_TIMER3_CC2(port, pin) SILABS_DBUS(port, pin, 117, 1, 2, 3)
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#define SILABS_DBUS_TIMER3_CDTI0(port, pin) SILABS_DBUS(port, pin, 117, 1, 3, 4)
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#define SILABS_DBUS_TIMER3_CDTI1(port, pin) SILABS_DBUS(port, pin, 117, 1, 4, 5)
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#define SILABS_DBUS_TIMER3_CDTI2(port, pin) SILABS_DBUS(port, pin, 117, 1, 5, 6)
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#define SILABS_DBUS_TIMER4_CC0(port, pin) SILABS_DBUS(port, pin, 125, 1, 0, 1)
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#define SILABS_DBUS_TIMER4_CC1(port, pin) SILABS_DBUS(port, pin, 125, 1, 1, 2)
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#define SILABS_DBUS_TIMER4_CC2(port, pin) SILABS_DBUS(port, pin, 125, 1, 2, 3)
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#define SILABS_DBUS_TIMER4_CDTI0(port, pin) SILABS_DBUS(port, pin, 125, 1, 3, 4)
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#define SILABS_DBUS_TIMER4_CDTI1(port, pin) SILABS_DBUS(port, pin, 125, 1, 4, 5)
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#define SILABS_DBUS_TIMER4_CDTI2(port, pin) SILABS_DBUS(port, pin, 125, 1, 5, 6)
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#define SILABS_DBUS_USART0_CS(port, pin) SILABS_DBUS(port, pin, 133, 1, 0, 1)
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#define SILABS_DBUS_USART0_RTS(port, pin) SILABS_DBUS(port, pin, 133, 1, 1, 3)
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#define SILABS_DBUS_USART0_RX(port, pin) SILABS_DBUS(port, pin, 133, 1, 2, 4)
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#define SILABS_DBUS_USART0_CLK(port, pin) SILABS_DBUS(port, pin, 133, 1, 3, 5)
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#define SILABS_DBUS_USART0_TX(port, pin) SILABS_DBUS(port, pin, 133, 1, 4, 6)
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#define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 133, 0, 0, 2)
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#define SILABS_DBUS_USART1_CS(port, pin) SILABS_DBUS(port, pin, 141, 1, 0, 1)
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#define SILABS_DBUS_USART1_RTS(port, pin) SILABS_DBUS(port, pin, 141, 1, 1, 3)
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#define SILABS_DBUS_USART1_RX(port, pin) SILABS_DBUS(port, pin, 141, 1, 2, 4)
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#define SILABS_DBUS_USART1_CLK(port, pin) SILABS_DBUS(port, pin, 141, 1, 3, 5)
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#define SILABS_DBUS_USART1_TX(port, pin) SILABS_DBUS(port, pin, 141, 1, 4, 6)
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#define SILABS_DBUS_USART1_CTS(port, pin) SILABS_DBUS(port, pin, 141, 0, 0, 2)
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#define GPIO_SWCLKTCK_PA1 SILABS_FIXED_ROUTE(0x0, 0x1, 0, 0)
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#define GPIO_SWDIOTMS_PA2 SILABS_FIXED_ROUTE(0x0, 0x2, 0, 1)
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#define GPIO_TDO_PA3 SILABS_FIXED_ROUTE(0x0, 0x3, 0, 2)
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#define GPIO_TDI_PA4 SILABS_FIXED_ROUTE(0x0, 0x4, 0, 3)
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#define GPIO_SWV_PA3 SILABS_FIXED_ROUTE(0x0, 0x3, 1, 0)
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#define GPIO_TRACECLK_PA4 SILABS_FIXED_ROUTE(0x0, 0x4, 1, 1)
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#define GPIO_TRACEDATA0_PA3 SILABS_FIXED_ROUTE(0x0, 0x3, 1, 2)
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#define GPIO_TRACEDATA1_PA5 SILABS_FIXED_ROUTE(0x0, 0x5, 1, 3)
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#define GPIO_TRACEDATA2_PA6 SILABS_FIXED_ROUTE(0x0, 0x6, 1, 4)
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#define GPIO_TRACEDATA3_PA7 SILABS_FIXED_ROUTE(0x0, 0x7, 1, 5)
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#define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0)
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#define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1)
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#define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
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#define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3)
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#define ACMP0_ACMPOUT_PA4 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x4)
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#define ACMP0_ACMPOUT_PA5 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x5)
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#define ACMP0_ACMPOUT_PA6 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x6)
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#define ACMP0_ACMPOUT_PA7 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x7)
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#define ACMP0_ACMPOUT_PA8 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x8)
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#define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0)
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#define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1)
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#define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2)
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#define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3)
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#define ACMP0_ACMPOUT_PB4 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x4)
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#define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0)
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#define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
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#define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2)
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#define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
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#define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4)
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#define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5)
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#define ACMP0_ACMPOUT_PC6 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x6)
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#define ACMP0_ACMPOUT_PC7 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x7)
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#define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0)
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#define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1)
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#define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2)
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#define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3)
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#define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0)
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#define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1)
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#define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2)
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#define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3)
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#define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4)
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#define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5)
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#define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6)
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#define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7)
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#define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0)
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#define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1)
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#define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2)
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#define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3)
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#define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0)
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#define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1)
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#define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2)
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#define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3)
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#define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4)
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#define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5)
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#define CMU_CLKOUT1_PC6 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x6)
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#define CMU_CLKOUT1_PC7 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x7)
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#define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0)
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#define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1)
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#define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2)
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#define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3)
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#define CMU_CLKOUT2_PA0 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x0)
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#define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1)
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#define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2)
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#define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3)
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#define CMU_CLKOUT2_PA4 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x4)
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#define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5)
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#define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6)
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#define CMU_CLKOUT2_PA7 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x7)
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#define CMU_CLKOUT2_PA8 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x8)
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#define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0)
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#define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1)
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#define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2)
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#define CMU_CLKOUT2_PB3 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x3)
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#define CMU_CLKOUT2_PB4 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x4)
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#define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0)
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#define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1)
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#define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2)
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#define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3)
217
#define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4)
218
#define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5)
219
#define CMU_CLKIN0_PC6 SILABS_DBUS_CMU_CLKIN0(0x2, 0x6)
220
#define CMU_CLKIN0_PC7 SILABS_DBUS_CMU_CLKIN0(0x2, 0x7)
221
#define CMU_CLKIN0_PD0 SILABS_DBUS_CMU_CLKIN0(0x3, 0x0)
222
#define CMU_CLKIN0_PD1 SILABS_DBUS_CMU_CLKIN0(0x3, 0x1)
223
#define CMU_CLKIN0_PD2 SILABS_DBUS_CMU_CLKIN0(0x3, 0x2)
224
#define CMU_CLKIN0_PD3 SILABS_DBUS_CMU_CLKIN0(0x3, 0x3)
225
226
#define EUSART0_CS_PA0 SILABS_DBUS_EUSART0_CS(0x0, 0x0)
227
#define EUSART0_CS_PA1 SILABS_DBUS_EUSART0_CS(0x0, 0x1)
228
#define EUSART0_CS_PA2 SILABS_DBUS_EUSART0_CS(0x0, 0x2)
229
#define EUSART0_CS_PA3 SILABS_DBUS_EUSART0_CS(0x0, 0x3)
230
#define EUSART0_CS_PA4 SILABS_DBUS_EUSART0_CS(0x0, 0x4)
231
#define EUSART0_CS_PA5 SILABS_DBUS_EUSART0_CS(0x0, 0x5)
232
#define EUSART0_CS_PA6 SILABS_DBUS_EUSART0_CS(0x0, 0x6)
233
#define EUSART0_CS_PA7 SILABS_DBUS_EUSART0_CS(0x0, 0x7)
234
#define EUSART0_CS_PA8 SILABS_DBUS_EUSART0_CS(0x0, 0x8)
235
#define EUSART0_CS_PB0 SILABS_DBUS_EUSART0_CS(0x1, 0x0)
236
#define EUSART0_CS_PB1 SILABS_DBUS_EUSART0_CS(0x1, 0x1)
237
#define EUSART0_CS_PB2 SILABS_DBUS_EUSART0_CS(0x1, 0x2)
238
#define EUSART0_CS_PB3 SILABS_DBUS_EUSART0_CS(0x1, 0x3)
239
#define EUSART0_CS_PB4 SILABS_DBUS_EUSART0_CS(0x1, 0x4)
240
#define EUSART0_CS_PC0 SILABS_DBUS_EUSART0_CS(0x2, 0x0)
241
#define EUSART0_CS_PC1 SILABS_DBUS_EUSART0_CS(0x2, 0x1)
242
#define EUSART0_CS_PC2 SILABS_DBUS_EUSART0_CS(0x2, 0x2)
243
#define EUSART0_CS_PC3 SILABS_DBUS_EUSART0_CS(0x2, 0x3)
244
#define EUSART0_CS_PC4 SILABS_DBUS_EUSART0_CS(0x2, 0x4)
245
#define EUSART0_CS_PC5 SILABS_DBUS_EUSART0_CS(0x2, 0x5)
246
#define EUSART0_CS_PC6 SILABS_DBUS_EUSART0_CS(0x2, 0x6)
247
#define EUSART0_CS_PC7 SILABS_DBUS_EUSART0_CS(0x2, 0x7)
248
#define EUSART0_CS_PD0 SILABS_DBUS_EUSART0_CS(0x3, 0x0)
249
#define EUSART0_CS_PD1 SILABS_DBUS_EUSART0_CS(0x3, 0x1)
250
#define EUSART0_CS_PD2 SILABS_DBUS_EUSART0_CS(0x3, 0x2)
251
#define EUSART0_CS_PD3 SILABS_DBUS_EUSART0_CS(0x3, 0x3)
252
#define EUSART0_RTS_PA0 SILABS_DBUS_EUSART0_RTS(0x0, 0x0)
253
#define EUSART0_RTS_PA1 SILABS_DBUS_EUSART0_RTS(0x0, 0x1)
254
#define EUSART0_RTS_PA2 SILABS_DBUS_EUSART0_RTS(0x0, 0x2)
255
#define EUSART0_RTS_PA3 SILABS_DBUS_EUSART0_RTS(0x0, 0x3)
256
#define EUSART0_RTS_PA4 SILABS_DBUS_EUSART0_RTS(0x0, 0x4)
257
#define EUSART0_RTS_PA5 SILABS_DBUS_EUSART0_RTS(0x0, 0x5)
258
#define EUSART0_RTS_PA6 SILABS_DBUS_EUSART0_RTS(0x0, 0x6)
259
#define EUSART0_RTS_PA7 SILABS_DBUS_EUSART0_RTS(0x0, 0x7)
260
#define EUSART0_RTS_PA8 SILABS_DBUS_EUSART0_RTS(0x0, 0x8)
261
#define EUSART0_RTS_PB0 SILABS_DBUS_EUSART0_RTS(0x1, 0x0)
262
#define EUSART0_RTS_PB1 SILABS_DBUS_EUSART0_RTS(0x1, 0x1)
263
#define EUSART0_RTS_PB2 SILABS_DBUS_EUSART0_RTS(0x1, 0x2)
264
#define EUSART0_RTS_PB3 SILABS_DBUS_EUSART0_RTS(0x1, 0x3)
265
#define EUSART0_RTS_PB4 SILABS_DBUS_EUSART0_RTS(0x1, 0x4)
266
#define EUSART0_RTS_PC0 SILABS_DBUS_EUSART0_RTS(0x2, 0x0)
267
#define EUSART0_RTS_PC1 SILABS_DBUS_EUSART0_RTS(0x2, 0x1)
268
#define EUSART0_RTS_PC2 SILABS_DBUS_EUSART0_RTS(0x2, 0x2)
269
#define EUSART0_RTS_PC3 SILABS_DBUS_EUSART0_RTS(0x2, 0x3)
270
#define EUSART0_RTS_PC4 SILABS_DBUS_EUSART0_RTS(0x2, 0x4)
271
#define EUSART0_RTS_PC5 SILABS_DBUS_EUSART0_RTS(0x2, 0x5)
272
#define EUSART0_RTS_PC6 SILABS_DBUS_EUSART0_RTS(0x2, 0x6)
273
#define EUSART0_RTS_PC7 SILABS_DBUS_EUSART0_RTS(0x2, 0x7)
274
#define EUSART0_RTS_PD0 SILABS_DBUS_EUSART0_RTS(0x3, 0x0)
275
#define EUSART0_RTS_PD1 SILABS_DBUS_EUSART0_RTS(0x3, 0x1)
276
#define EUSART0_RTS_PD2 SILABS_DBUS_EUSART0_RTS(0x3, 0x2)
277
#define EUSART0_RTS_PD3 SILABS_DBUS_EUSART0_RTS(0x3, 0x3)
278
#define EUSART0_RX_PA0 SILABS_DBUS_EUSART0_RX(0x0, 0x0)
279
#define EUSART0_RX_PA1 SILABS_DBUS_EUSART0_RX(0x0, 0x1)
280
#define EUSART0_RX_PA2 SILABS_DBUS_EUSART0_RX(0x0, 0x2)
281
#define EUSART0_RX_PA3 SILABS_DBUS_EUSART0_RX(0x0, 0x3)
282
#define EUSART0_RX_PA4 SILABS_DBUS_EUSART0_RX(0x0, 0x4)
283
#define EUSART0_RX_PA5 SILABS_DBUS_EUSART0_RX(0x0, 0x5)
284
#define EUSART0_RX_PA6 SILABS_DBUS_EUSART0_RX(0x0, 0x6)
285
#define EUSART0_RX_PA7 SILABS_DBUS_EUSART0_RX(0x0, 0x7)
286
#define EUSART0_RX_PA8 SILABS_DBUS_EUSART0_RX(0x0, 0x8)
287
#define EUSART0_RX_PB0 SILABS_DBUS_EUSART0_RX(0x1, 0x0)
288
#define EUSART0_RX_PB1 SILABS_DBUS_EUSART0_RX(0x1, 0x1)
289
#define EUSART0_RX_PB2 SILABS_DBUS_EUSART0_RX(0x1, 0x2)
290
#define EUSART0_RX_PB3 SILABS_DBUS_EUSART0_RX(0x1, 0x3)
291
#define EUSART0_RX_PB4 SILABS_DBUS_EUSART0_RX(0x1, 0x4)
292
#define EUSART0_RX_PC0 SILABS_DBUS_EUSART0_RX(0x2, 0x0)
293
#define EUSART0_RX_PC1 SILABS_DBUS_EUSART0_RX(0x2, 0x1)
294
#define EUSART0_RX_PC2 SILABS_DBUS_EUSART0_RX(0x2, 0x2)
295
#define EUSART0_RX_PC3 SILABS_DBUS_EUSART0_RX(0x2, 0x3)
296
#define EUSART0_RX_PC4 SILABS_DBUS_EUSART0_RX(0x2, 0x4)
297
#define EUSART0_RX_PC5 SILABS_DBUS_EUSART0_RX(0x2, 0x5)
298
#define EUSART0_RX_PC6 SILABS_DBUS_EUSART0_RX(0x2, 0x6)
299
#define EUSART0_RX_PC7 SILABS_DBUS_EUSART0_RX(0x2, 0x7)
300
#define EUSART0_RX_PD0 SILABS_DBUS_EUSART0_RX(0x3, 0x0)
301
#define EUSART0_RX_PD1 SILABS_DBUS_EUSART0_RX(0x3, 0x1)
302
#define EUSART0_RX_PD2 SILABS_DBUS_EUSART0_RX(0x3, 0x2)
303
#define EUSART0_RX_PD3 SILABS_DBUS_EUSART0_RX(0x3, 0x3)
304
#define EUSART0_SCLK_PA0 SILABS_DBUS_EUSART0_SCLK(0x0, 0x0)
305
#define EUSART0_SCLK_PA1 SILABS_DBUS_EUSART0_SCLK(0x0, 0x1)
306
#define EUSART0_SCLK_PA2 SILABS_DBUS_EUSART0_SCLK(0x0, 0x2)
307
#define EUSART0_SCLK_PA3 SILABS_DBUS_EUSART0_SCLK(0x0, 0x3)
308
#define EUSART0_SCLK_PA4 SILABS_DBUS_EUSART0_SCLK(0x0, 0x4)
309
#define EUSART0_SCLK_PA5 SILABS_DBUS_EUSART0_SCLK(0x0, 0x5)
310
#define EUSART0_SCLK_PA6 SILABS_DBUS_EUSART0_SCLK(0x0, 0x6)
311
#define EUSART0_SCLK_PA7 SILABS_DBUS_EUSART0_SCLK(0x0, 0x7)
312
#define EUSART0_SCLK_PA8 SILABS_DBUS_EUSART0_SCLK(0x0, 0x8)
313
#define EUSART0_SCLK_PB0 SILABS_DBUS_EUSART0_SCLK(0x1, 0x0)
314
#define EUSART0_SCLK_PB1 SILABS_DBUS_EUSART0_SCLK(0x1, 0x1)
315
#define EUSART0_SCLK_PB2 SILABS_DBUS_EUSART0_SCLK(0x1, 0x2)
316
#define EUSART0_SCLK_PB3 SILABS_DBUS_EUSART0_SCLK(0x1, 0x3)
317
#define EUSART0_SCLK_PB4 SILABS_DBUS_EUSART0_SCLK(0x1, 0x4)
318
#define EUSART0_SCLK_PC0 SILABS_DBUS_EUSART0_SCLK(0x2, 0x0)
319
#define EUSART0_SCLK_PC1 SILABS_DBUS_EUSART0_SCLK(0x2, 0x1)
320
#define EUSART0_SCLK_PC2 SILABS_DBUS_EUSART0_SCLK(0x2, 0x2)
321
#define EUSART0_SCLK_PC3 SILABS_DBUS_EUSART0_SCLK(0x2, 0x3)
322
#define EUSART0_SCLK_PC4 SILABS_DBUS_EUSART0_SCLK(0x2, 0x4)
323
#define EUSART0_SCLK_PC5 SILABS_DBUS_EUSART0_SCLK(0x2, 0x5)
324
#define EUSART0_SCLK_PC6 SILABS_DBUS_EUSART0_SCLK(0x2, 0x6)
325
#define EUSART0_SCLK_PC7 SILABS_DBUS_EUSART0_SCLK(0x2, 0x7)
326
#define EUSART0_SCLK_PD0 SILABS_DBUS_EUSART0_SCLK(0x3, 0x0)
327
#define EUSART0_SCLK_PD1 SILABS_DBUS_EUSART0_SCLK(0x3, 0x1)
328
#define EUSART0_SCLK_PD2 SILABS_DBUS_EUSART0_SCLK(0x3, 0x2)
329
#define EUSART0_SCLK_PD3 SILABS_DBUS_EUSART0_SCLK(0x3, 0x3)
330
#define EUSART0_TX_PA0 SILABS_DBUS_EUSART0_TX(0x0, 0x0)
331
#define EUSART0_TX_PA1 SILABS_DBUS_EUSART0_TX(0x0, 0x1)
332
#define EUSART0_TX_PA2 SILABS_DBUS_EUSART0_TX(0x0, 0x2)
333
#define EUSART0_TX_PA3 SILABS_DBUS_EUSART0_TX(0x0, 0x3)
334
#define EUSART0_TX_PA4 SILABS_DBUS_EUSART0_TX(0x0, 0x4)
335
#define EUSART0_TX_PA5 SILABS_DBUS_EUSART0_TX(0x0, 0x5)
336
#define EUSART0_TX_PA6 SILABS_DBUS_EUSART0_TX(0x0, 0x6)
337
#define EUSART0_TX_PA7 SILABS_DBUS_EUSART0_TX(0x0, 0x7)
338
#define EUSART0_TX_PA8 SILABS_DBUS_EUSART0_TX(0x0, 0x8)
339
#define EUSART0_TX_PB0 SILABS_DBUS_EUSART0_TX(0x1, 0x0)
340
#define EUSART0_TX_PB1 SILABS_DBUS_EUSART0_TX(0x1, 0x1)
341
#define EUSART0_TX_PB2 SILABS_DBUS_EUSART0_TX(0x1, 0x2)
342
#define EUSART0_TX_PB3 SILABS_DBUS_EUSART0_TX(0x1, 0x3)
343
#define EUSART0_TX_PB4 SILABS_DBUS_EUSART0_TX(0x1, 0x4)
344
#define EUSART0_TX_PC0 SILABS_DBUS_EUSART0_TX(0x2, 0x0)
345
#define EUSART0_TX_PC1 SILABS_DBUS_EUSART0_TX(0x2, 0x1)
346
#define EUSART0_TX_PC2 SILABS_DBUS_EUSART0_TX(0x2, 0x2)
347
#define EUSART0_TX_PC3 SILABS_DBUS_EUSART0_TX(0x2, 0x3)
348
#define EUSART0_TX_PC4 SILABS_DBUS_EUSART0_TX(0x2, 0x4)
349
#define EUSART0_TX_PC5 SILABS_DBUS_EUSART0_TX(0x2, 0x5)
350
#define EUSART0_TX_PC6 SILABS_DBUS_EUSART0_TX(0x2, 0x6)
351
#define EUSART0_TX_PC7 SILABS_DBUS_EUSART0_TX(0x2, 0x7)
352
#define EUSART0_TX_PD0 SILABS_DBUS_EUSART0_TX(0x3, 0x0)
353
#define EUSART0_TX_PD1 SILABS_DBUS_EUSART0_TX(0x3, 0x1)
354
#define EUSART0_TX_PD2 SILABS_DBUS_EUSART0_TX(0x3, 0x2)
355
#define EUSART0_TX_PD3 SILABS_DBUS_EUSART0_TX(0x3, 0x3)
356
#define EUSART0_CTS_PA0 SILABS_DBUS_EUSART0_CTS(0x0, 0x0)
357
#define EUSART0_CTS_PA1 SILABS_DBUS_EUSART0_CTS(0x0, 0x1)
358
#define EUSART0_CTS_PA2 SILABS_DBUS_EUSART0_CTS(0x0, 0x2)
359
#define EUSART0_CTS_PA3 SILABS_DBUS_EUSART0_CTS(0x0, 0x3)
360
#define EUSART0_CTS_PA4 SILABS_DBUS_EUSART0_CTS(0x0, 0x4)
361
#define EUSART0_CTS_PA5 SILABS_DBUS_EUSART0_CTS(0x0, 0x5)
362
#define EUSART0_CTS_PA6 SILABS_DBUS_EUSART0_CTS(0x0, 0x6)
363
#define EUSART0_CTS_PA7 SILABS_DBUS_EUSART0_CTS(0x0, 0x7)
364
#define EUSART0_CTS_PA8 SILABS_DBUS_EUSART0_CTS(0x0, 0x8)
365
#define EUSART0_CTS_PB0 SILABS_DBUS_EUSART0_CTS(0x1, 0x0)
366
#define EUSART0_CTS_PB1 SILABS_DBUS_EUSART0_CTS(0x1, 0x1)
367
#define EUSART0_CTS_PB2 SILABS_DBUS_EUSART0_CTS(0x1, 0x2)
368
#define EUSART0_CTS_PB3 SILABS_DBUS_EUSART0_CTS(0x1, 0x3)
369
#define EUSART0_CTS_PB4 SILABS_DBUS_EUSART0_CTS(0x1, 0x4)
370
#define EUSART0_CTS_PC0 SILABS_DBUS_EUSART0_CTS(0x2, 0x0)
371
#define EUSART0_CTS_PC1 SILABS_DBUS_EUSART0_CTS(0x2, 0x1)
372
#define EUSART0_CTS_PC2 SILABS_DBUS_EUSART0_CTS(0x2, 0x2)
373
#define EUSART0_CTS_PC3 SILABS_DBUS_EUSART0_CTS(0x2, 0x3)
374
#define EUSART0_CTS_PC4 SILABS_DBUS_EUSART0_CTS(0x2, 0x4)
375
#define EUSART0_CTS_PC5 SILABS_DBUS_EUSART0_CTS(0x2, 0x5)
376
#define EUSART0_CTS_PC6 SILABS_DBUS_EUSART0_CTS(0x2, 0x6)
377
#define EUSART0_CTS_PC7 SILABS_DBUS_EUSART0_CTS(0x2, 0x7)
378
#define EUSART0_CTS_PD0 SILABS_DBUS_EUSART0_CTS(0x3, 0x0)
379
#define EUSART0_CTS_PD1 SILABS_DBUS_EUSART0_CTS(0x3, 0x1)
380
#define EUSART0_CTS_PD2 SILABS_DBUS_EUSART0_CTS(0x3, 0x2)
381
#define EUSART0_CTS_PD3 SILABS_DBUS_EUSART0_CTS(0x3, 0x3)
382
383
#define EUSART1_CS_PA0 SILABS_DBUS_EUSART1_CS(0x0, 0x0)
384
#define EUSART1_CS_PA1 SILABS_DBUS_EUSART1_CS(0x0, 0x1)
385
#define EUSART1_CS_PA2 SILABS_DBUS_EUSART1_CS(0x0, 0x2)
386
#define EUSART1_CS_PA3 SILABS_DBUS_EUSART1_CS(0x0, 0x3)
387
#define EUSART1_CS_PA4 SILABS_DBUS_EUSART1_CS(0x0, 0x4)
388
#define EUSART1_CS_PA5 SILABS_DBUS_EUSART1_CS(0x0, 0x5)
389
#define EUSART1_CS_PA6 SILABS_DBUS_EUSART1_CS(0x0, 0x6)
390
#define EUSART1_CS_PA7 SILABS_DBUS_EUSART1_CS(0x0, 0x7)
391
#define EUSART1_CS_PA8 SILABS_DBUS_EUSART1_CS(0x0, 0x8)
392
#define EUSART1_CS_PB0 SILABS_DBUS_EUSART1_CS(0x1, 0x0)
393
#define EUSART1_CS_PB1 SILABS_DBUS_EUSART1_CS(0x1, 0x1)
394
#define EUSART1_CS_PB2 SILABS_DBUS_EUSART1_CS(0x1, 0x2)
395
#define EUSART1_CS_PB3 SILABS_DBUS_EUSART1_CS(0x1, 0x3)
396
#define EUSART1_CS_PB4 SILABS_DBUS_EUSART1_CS(0x1, 0x4)
397
#define EUSART1_CS_PC0 SILABS_DBUS_EUSART1_CS(0x2, 0x0)
398
#define EUSART1_CS_PC1 SILABS_DBUS_EUSART1_CS(0x2, 0x1)
399
#define EUSART1_CS_PC2 SILABS_DBUS_EUSART1_CS(0x2, 0x2)
400
#define EUSART1_CS_PC3 SILABS_DBUS_EUSART1_CS(0x2, 0x3)
401
#define EUSART1_CS_PC4 SILABS_DBUS_EUSART1_CS(0x2, 0x4)
402
#define EUSART1_CS_PC5 SILABS_DBUS_EUSART1_CS(0x2, 0x5)
403
#define EUSART1_CS_PC6 SILABS_DBUS_EUSART1_CS(0x2, 0x6)
404
#define EUSART1_CS_PC7 SILABS_DBUS_EUSART1_CS(0x2, 0x7)
405
#define EUSART1_CS_PD0 SILABS_DBUS_EUSART1_CS(0x3, 0x0)
406
#define EUSART1_CS_PD1 SILABS_DBUS_EUSART1_CS(0x3, 0x1)
407
#define EUSART1_CS_PD2 SILABS_DBUS_EUSART1_CS(0x3, 0x2)
408
#define EUSART1_CS_PD3 SILABS_DBUS_EUSART1_CS(0x3, 0x3)
409
#define EUSART1_RTS_PA0 SILABS_DBUS_EUSART1_RTS(0x0, 0x0)
410
#define EUSART1_RTS_PA1 SILABS_DBUS_EUSART1_RTS(0x0, 0x1)
411
#define EUSART1_RTS_PA2 SILABS_DBUS_EUSART1_RTS(0x0, 0x2)
412
#define EUSART1_RTS_PA3 SILABS_DBUS_EUSART1_RTS(0x0, 0x3)
413
#define EUSART1_RTS_PA4 SILABS_DBUS_EUSART1_RTS(0x0, 0x4)
414
#define EUSART1_RTS_PA5 SILABS_DBUS_EUSART1_RTS(0x0, 0x5)
415
#define EUSART1_RTS_PA6 SILABS_DBUS_EUSART1_RTS(0x0, 0x6)
416
#define EUSART1_RTS_PA7 SILABS_DBUS_EUSART1_RTS(0x0, 0x7)
417
#define EUSART1_RTS_PA8 SILABS_DBUS_EUSART1_RTS(0x0, 0x8)
418
#define EUSART1_RTS_PB0 SILABS_DBUS_EUSART1_RTS(0x1, 0x0)
419
#define EUSART1_RTS_PB1 SILABS_DBUS_EUSART1_RTS(0x1, 0x1)
420
#define EUSART1_RTS_PB2 SILABS_DBUS_EUSART1_RTS(0x1, 0x2)
421
#define EUSART1_RTS_PB3 SILABS_DBUS_EUSART1_RTS(0x1, 0x3)
422
#define EUSART1_RTS_PB4 SILABS_DBUS_EUSART1_RTS(0x1, 0x4)
423
#define EUSART1_RTS_PC0 SILABS_DBUS_EUSART1_RTS(0x2, 0x0)
424
#define EUSART1_RTS_PC1 SILABS_DBUS_EUSART1_RTS(0x2, 0x1)
425
#define EUSART1_RTS_PC2 SILABS_DBUS_EUSART1_RTS(0x2, 0x2)
426
#define EUSART1_RTS_PC3 SILABS_DBUS_EUSART1_RTS(0x2, 0x3)
427
#define EUSART1_RTS_PC4 SILABS_DBUS_EUSART1_RTS(0x2, 0x4)
428
#define EUSART1_RTS_PC5 SILABS_DBUS_EUSART1_RTS(0x2, 0x5)
429
#define EUSART1_RTS_PC6 SILABS_DBUS_EUSART1_RTS(0x2, 0x6)
430
#define EUSART1_RTS_PC7 SILABS_DBUS_EUSART1_RTS(0x2, 0x7)
431
#define EUSART1_RTS_PD0 SILABS_DBUS_EUSART1_RTS(0x3, 0x0)
432
#define EUSART1_RTS_PD1 SILABS_DBUS_EUSART1_RTS(0x3, 0x1)
433
#define EUSART1_RTS_PD2 SILABS_DBUS_EUSART1_RTS(0x3, 0x2)
434
#define EUSART1_RTS_PD3 SILABS_DBUS_EUSART1_RTS(0x3, 0x3)
435
#define EUSART1_RX_PA0 SILABS_DBUS_EUSART1_RX(0x0, 0x0)
436
#define EUSART1_RX_PA1 SILABS_DBUS_EUSART1_RX(0x0, 0x1)
437
#define EUSART1_RX_PA2 SILABS_DBUS_EUSART1_RX(0x0, 0x2)
438
#define EUSART1_RX_PA3 SILABS_DBUS_EUSART1_RX(0x0, 0x3)
439
#define EUSART1_RX_PA4 SILABS_DBUS_EUSART1_RX(0x0, 0x4)
440
#define EUSART1_RX_PA5 SILABS_DBUS_EUSART1_RX(0x0, 0x5)
441
#define EUSART1_RX_PA6 SILABS_DBUS_EUSART1_RX(0x0, 0x6)
442
#define EUSART1_RX_PA7 SILABS_DBUS_EUSART1_RX(0x0, 0x7)
443
#define EUSART1_RX_PA8 SILABS_DBUS_EUSART1_RX(0x0, 0x8)
444
#define EUSART1_RX_PB0 SILABS_DBUS_EUSART1_RX(0x1, 0x0)
445
#define EUSART1_RX_PB1 SILABS_DBUS_EUSART1_RX(0x1, 0x1)
446
#define EUSART1_RX_PB2 SILABS_DBUS_EUSART1_RX(0x1, 0x2)
447
#define EUSART1_RX_PB3 SILABS_DBUS_EUSART1_RX(0x1, 0x3)
448
#define EUSART1_RX_PB4 SILABS_DBUS_EUSART1_RX(0x1, 0x4)
449
#define EUSART1_RX_PC0 SILABS_DBUS_EUSART1_RX(0x2, 0x0)
450
#define EUSART1_RX_PC1 SILABS_DBUS_EUSART1_RX(0x2, 0x1)
451
#define EUSART1_RX_PC2 SILABS_DBUS_EUSART1_RX(0x2, 0x2)
452
#define EUSART1_RX_PC3 SILABS_DBUS_EUSART1_RX(0x2, 0x3)
453
#define EUSART1_RX_PC4 SILABS_DBUS_EUSART1_RX(0x2, 0x4)
454
#define EUSART1_RX_PC5 SILABS_DBUS_EUSART1_RX(0x2, 0x5)
455
#define EUSART1_RX_PC6 SILABS_DBUS_EUSART1_RX(0x2, 0x6)
456
#define EUSART1_RX_PC7 SILABS_DBUS_EUSART1_RX(0x2, 0x7)
457
#define EUSART1_RX_PD0 SILABS_DBUS_EUSART1_RX(0x3, 0x0)
458
#define EUSART1_RX_PD1 SILABS_DBUS_EUSART1_RX(0x3, 0x1)
459
#define EUSART1_RX_PD2 SILABS_DBUS_EUSART1_RX(0x3, 0x2)
460
#define EUSART1_RX_PD3 SILABS_DBUS_EUSART1_RX(0x3, 0x3)
461
#define EUSART1_SCLK_PA0 SILABS_DBUS_EUSART1_SCLK(0x0, 0x0)
462
#define EUSART1_SCLK_PA1 SILABS_DBUS_EUSART1_SCLK(0x0, 0x1)
463
#define EUSART1_SCLK_PA2 SILABS_DBUS_EUSART1_SCLK(0x0, 0x2)
464
#define EUSART1_SCLK_PA3 SILABS_DBUS_EUSART1_SCLK(0x0, 0x3)
465
#define EUSART1_SCLK_PA4 SILABS_DBUS_EUSART1_SCLK(0x0, 0x4)
466
#define EUSART1_SCLK_PA5 SILABS_DBUS_EUSART1_SCLK(0x0, 0x5)
467
#define EUSART1_SCLK_PA6 SILABS_DBUS_EUSART1_SCLK(0x0, 0x6)
468
#define EUSART1_SCLK_PA7 SILABS_DBUS_EUSART1_SCLK(0x0, 0x7)
469
#define EUSART1_SCLK_PA8 SILABS_DBUS_EUSART1_SCLK(0x0, 0x8)
470
#define EUSART1_SCLK_PB0 SILABS_DBUS_EUSART1_SCLK(0x1, 0x0)
471
#define EUSART1_SCLK_PB1 SILABS_DBUS_EUSART1_SCLK(0x1, 0x1)
472
#define EUSART1_SCLK_PB2 SILABS_DBUS_EUSART1_SCLK(0x1, 0x2)
473
#define EUSART1_SCLK_PB3 SILABS_DBUS_EUSART1_SCLK(0x1, 0x3)
474
#define EUSART1_SCLK_PB4 SILABS_DBUS_EUSART1_SCLK(0x1, 0x4)
475
#define EUSART1_SCLK_PC0 SILABS_DBUS_EUSART1_SCLK(0x2, 0x0)
476
#define EUSART1_SCLK_PC1 SILABS_DBUS_EUSART1_SCLK(0x2, 0x1)
477
#define EUSART1_SCLK_PC2 SILABS_DBUS_EUSART1_SCLK(0x2, 0x2)
478
#define EUSART1_SCLK_PC3 SILABS_DBUS_EUSART1_SCLK(0x2, 0x3)
479
#define EUSART1_SCLK_PC4 SILABS_DBUS_EUSART1_SCLK(0x2, 0x4)
480
#define EUSART1_SCLK_PC5 SILABS_DBUS_EUSART1_SCLK(0x2, 0x5)
481
#define EUSART1_SCLK_PC6 SILABS_DBUS_EUSART1_SCLK(0x2, 0x6)
482
#define EUSART1_SCLK_PC7 SILABS_DBUS_EUSART1_SCLK(0x2, 0x7)
483
#define EUSART1_SCLK_PD0 SILABS_DBUS_EUSART1_SCLK(0x3, 0x0)
484
#define EUSART1_SCLK_PD1 SILABS_DBUS_EUSART1_SCLK(0x3, 0x1)
485
#define EUSART1_SCLK_PD2 SILABS_DBUS_EUSART1_SCLK(0x3, 0x2)
486
#define EUSART1_SCLK_PD3 SILABS_DBUS_EUSART1_SCLK(0x3, 0x3)
487
#define EUSART1_TX_PA0 SILABS_DBUS_EUSART1_TX(0x0, 0x0)
488
#define EUSART1_TX_PA1 SILABS_DBUS_EUSART1_TX(0x0, 0x1)
489
#define EUSART1_TX_PA2 SILABS_DBUS_EUSART1_TX(0x0, 0x2)
490
#define EUSART1_TX_PA3 SILABS_DBUS_EUSART1_TX(0x0, 0x3)
491
#define EUSART1_TX_PA4 SILABS_DBUS_EUSART1_TX(0x0, 0x4)
492
#define EUSART1_TX_PA5 SILABS_DBUS_EUSART1_TX(0x0, 0x5)
493
#define EUSART1_TX_PA6 SILABS_DBUS_EUSART1_TX(0x0, 0x6)
494
#define EUSART1_TX_PA7 SILABS_DBUS_EUSART1_TX(0x0, 0x7)
495
#define EUSART1_TX_PA8 SILABS_DBUS_EUSART1_TX(0x0, 0x8)
496
#define EUSART1_TX_PB0 SILABS_DBUS_EUSART1_TX(0x1, 0x0)
497
#define EUSART1_TX_PB1 SILABS_DBUS_EUSART1_TX(0x1, 0x1)
498
#define EUSART1_TX_PB2 SILABS_DBUS_EUSART1_TX(0x1, 0x2)
499
#define EUSART1_TX_PB3 SILABS_DBUS_EUSART1_TX(0x1, 0x3)
500
#define EUSART1_TX_PB4 SILABS_DBUS_EUSART1_TX(0x1, 0x4)
501
#define EUSART1_TX_PC0 SILABS_DBUS_EUSART1_TX(0x2, 0x0)
502
#define EUSART1_TX_PC1 SILABS_DBUS_EUSART1_TX(0x2, 0x1)
503
#define EUSART1_TX_PC2 SILABS_DBUS_EUSART1_TX(0x2, 0x2)
504
#define EUSART1_TX_PC3 SILABS_DBUS_EUSART1_TX(0x2, 0x3)
505
#define EUSART1_TX_PC4 SILABS_DBUS_EUSART1_TX(0x2, 0x4)
506
#define EUSART1_TX_PC5 SILABS_DBUS_EUSART1_TX(0x2, 0x5)
507
#define EUSART1_TX_PC6 SILABS_DBUS_EUSART1_TX(0x2, 0x6)
508
#define EUSART1_TX_PC7 SILABS_DBUS_EUSART1_TX(0x2, 0x7)
509
#define EUSART1_TX_PD0 SILABS_DBUS_EUSART1_TX(0x3, 0x0)
510
#define EUSART1_TX_PD1 SILABS_DBUS_EUSART1_TX(0x3, 0x1)
511
#define EUSART1_TX_PD2 SILABS_DBUS_EUSART1_TX(0x3, 0x2)
512
#define EUSART1_TX_PD3 SILABS_DBUS_EUSART1_TX(0x3, 0x3)
513
#define EUSART1_CTS_PA0 SILABS_DBUS_EUSART1_CTS(0x0, 0x0)
514
#define EUSART1_CTS_PA1 SILABS_DBUS_EUSART1_CTS(0x0, 0x1)
515
#define EUSART1_CTS_PA2 SILABS_DBUS_EUSART1_CTS(0x0, 0x2)
516
#define EUSART1_CTS_PA3 SILABS_DBUS_EUSART1_CTS(0x0, 0x3)
517
#define EUSART1_CTS_PA4 SILABS_DBUS_EUSART1_CTS(0x0, 0x4)
518
#define EUSART1_CTS_PA5 SILABS_DBUS_EUSART1_CTS(0x0, 0x5)
519
#define EUSART1_CTS_PA6 SILABS_DBUS_EUSART1_CTS(0x0, 0x6)
520
#define EUSART1_CTS_PA7 SILABS_DBUS_EUSART1_CTS(0x0, 0x7)
521
#define EUSART1_CTS_PA8 SILABS_DBUS_EUSART1_CTS(0x0, 0x8)
522
#define EUSART1_CTS_PB0 SILABS_DBUS_EUSART1_CTS(0x1, 0x0)
523
#define EUSART1_CTS_PB1 SILABS_DBUS_EUSART1_CTS(0x1, 0x1)
524
#define EUSART1_CTS_PB2 SILABS_DBUS_EUSART1_CTS(0x1, 0x2)
525
#define EUSART1_CTS_PB3 SILABS_DBUS_EUSART1_CTS(0x1, 0x3)
526
#define EUSART1_CTS_PB4 SILABS_DBUS_EUSART1_CTS(0x1, 0x4)
527
#define EUSART1_CTS_PC0 SILABS_DBUS_EUSART1_CTS(0x2, 0x0)
528
#define EUSART1_CTS_PC1 SILABS_DBUS_EUSART1_CTS(0x2, 0x1)
529
#define EUSART1_CTS_PC2 SILABS_DBUS_EUSART1_CTS(0x2, 0x2)
530
#define EUSART1_CTS_PC3 SILABS_DBUS_EUSART1_CTS(0x2, 0x3)
531
#define EUSART1_CTS_PC4 SILABS_DBUS_EUSART1_CTS(0x2, 0x4)
532
#define EUSART1_CTS_PC5 SILABS_DBUS_EUSART1_CTS(0x2, 0x5)
533
#define EUSART1_CTS_PC6 SILABS_DBUS_EUSART1_CTS(0x2, 0x6)
534
#define EUSART1_CTS_PC7 SILABS_DBUS_EUSART1_CTS(0x2, 0x7)
535
#define EUSART1_CTS_PD0 SILABS_DBUS_EUSART1_CTS(0x3, 0x0)
536
#define EUSART1_CTS_PD1 SILABS_DBUS_EUSART1_CTS(0x3, 0x1)
537
#define EUSART1_CTS_PD2 SILABS_DBUS_EUSART1_CTS(0x3, 0x2)
538
#define EUSART1_CTS_PD3 SILABS_DBUS_EUSART1_CTS(0x3, 0x3)
539
540
#define PTI_DCLK_PC0 SILABS_DBUS_PTI_DCLK(0x2, 0x0)
541
#define PTI_DCLK_PC1 SILABS_DBUS_PTI_DCLK(0x2, 0x1)
542
#define PTI_DCLK_PC2 SILABS_DBUS_PTI_DCLK(0x2, 0x2)
543
#define PTI_DCLK_PC3 SILABS_DBUS_PTI_DCLK(0x2, 0x3)
544
#define PTI_DCLK_PC4 SILABS_DBUS_PTI_DCLK(0x2, 0x4)
545
#define PTI_DCLK_PC5 SILABS_DBUS_PTI_DCLK(0x2, 0x5)
546
#define PTI_DCLK_PC6 SILABS_DBUS_PTI_DCLK(0x2, 0x6)
547
#define PTI_DCLK_PC7 SILABS_DBUS_PTI_DCLK(0x2, 0x7)
548
#define PTI_DCLK_PD0 SILABS_DBUS_PTI_DCLK(0x3, 0x0)
549
#define PTI_DCLK_PD1 SILABS_DBUS_PTI_DCLK(0x3, 0x1)
550
#define PTI_DCLK_PD2 SILABS_DBUS_PTI_DCLK(0x3, 0x2)
551
#define PTI_DCLK_PD3 SILABS_DBUS_PTI_DCLK(0x3, 0x3)
552
#define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0)
553
#define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1)
554
#define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2)
555
#define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3)
556
#define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4)
557
#define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5)
558
#define PTI_DFRAME_PC6 SILABS_DBUS_PTI_DFRAME(0x2, 0x6)
559
#define PTI_DFRAME_PC7 SILABS_DBUS_PTI_DFRAME(0x2, 0x7)
560
#define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0)
561
#define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1)
562
#define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2)
563
#define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3)
564
#define PTI_DOUT_PC0 SILABS_DBUS_PTI_DOUT(0x2, 0x0)
565
#define PTI_DOUT_PC1 SILABS_DBUS_PTI_DOUT(0x2, 0x1)
566
#define PTI_DOUT_PC2 SILABS_DBUS_PTI_DOUT(0x2, 0x2)
567
#define PTI_DOUT_PC3 SILABS_DBUS_PTI_DOUT(0x2, 0x3)
568
#define PTI_DOUT_PC4 SILABS_DBUS_PTI_DOUT(0x2, 0x4)
569
#define PTI_DOUT_PC5 SILABS_DBUS_PTI_DOUT(0x2, 0x5)
570
#define PTI_DOUT_PC6 SILABS_DBUS_PTI_DOUT(0x2, 0x6)
571
#define PTI_DOUT_PC7 SILABS_DBUS_PTI_DOUT(0x2, 0x7)
572
#define PTI_DOUT_PD0 SILABS_DBUS_PTI_DOUT(0x3, 0x0)
573
#define PTI_DOUT_PD1 SILABS_DBUS_PTI_DOUT(0x3, 0x1)
574
#define PTI_DOUT_PD2 SILABS_DBUS_PTI_DOUT(0x3, 0x2)
575
#define PTI_DOUT_PD3 SILABS_DBUS_PTI_DOUT(0x3, 0x3)
576
577
#define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0)
578
#define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1)
579
#define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2)
580
#define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3)
581
#define I2C0_SCL_PA4 SILABS_DBUS_I2C0_SCL(0x0, 0x4)
582
#define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5)
583
#define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6)
584
#define I2C0_SCL_PA7 SILABS_DBUS_I2C0_SCL(0x0, 0x7)
585
#define I2C0_SCL_PA8 SILABS_DBUS_I2C0_SCL(0x0, 0x8)
586
#define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0)
587
#define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1)
588
#define I2C0_SCL_PB2 SILABS_DBUS_I2C0_SCL(0x1, 0x2)
589
#define I2C0_SCL_PB3 SILABS_DBUS_I2C0_SCL(0x1, 0x3)
590
#define I2C0_SCL_PB4 SILABS_DBUS_I2C0_SCL(0x1, 0x4)
591
#define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0)
592
#define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1)
593
#define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2)
594
#define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3)
595
#define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4)
596
#define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5)
597
#define I2C0_SCL_PC6 SILABS_DBUS_I2C0_SCL(0x2, 0x6)
598
#define I2C0_SCL_PC7 SILABS_DBUS_I2C0_SCL(0x2, 0x7)
599
#define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0)
600
#define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1)
601
#define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2)
602
#define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3)
603
#define I2C0_SDA_PA0 SILABS_DBUS_I2C0_SDA(0x0, 0x0)
604
#define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1)
605
#define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2)
606
#define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3)
607
#define I2C0_SDA_PA4 SILABS_DBUS_I2C0_SDA(0x0, 0x4)
608
#define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5)
609
#define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6)
610
#define I2C0_SDA_PA7 SILABS_DBUS_I2C0_SDA(0x0, 0x7)
611
#define I2C0_SDA_PA8 SILABS_DBUS_I2C0_SDA(0x0, 0x8)
612
#define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0)
613
#define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1)
614
#define I2C0_SDA_PB2 SILABS_DBUS_I2C0_SDA(0x1, 0x2)
615
#define I2C0_SDA_PB3 SILABS_DBUS_I2C0_SDA(0x1, 0x3)
616
#define I2C0_SDA_PB4 SILABS_DBUS_I2C0_SDA(0x1, 0x4)
617
#define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0)
618
#define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1)
619
#define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2)
620
#define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3)
621
#define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4)
622
#define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5)
623
#define I2C0_SDA_PC6 SILABS_DBUS_I2C0_SDA(0x2, 0x6)
624
#define I2C0_SDA_PC7 SILABS_DBUS_I2C0_SDA(0x2, 0x7)
625
#define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0)
626
#define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1)
627
#define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2)
628
#define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3)
629
630
#define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0)
631
#define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1)
632
#define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2)
633
#define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3)
634
#define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4)
635
#define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5)
636
#define I2C1_SCL_PC6 SILABS_DBUS_I2C1_SCL(0x2, 0x6)
637
#define I2C1_SCL_PC7 SILABS_DBUS_I2C1_SCL(0x2, 0x7)
638
#define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0)
639
#define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1)
640
#define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2)
641
#define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3)
642
#define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0)
643
#define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1)
644
#define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2)
645
#define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3)
646
#define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4)
647
#define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5)
648
#define I2C1_SDA_PC6 SILABS_DBUS_I2C1_SDA(0x2, 0x6)
649
#define I2C1_SDA_PC7 SILABS_DBUS_I2C1_SDA(0x2, 0x7)
650
#define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0)
651
#define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1)
652
#define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2)
653
#define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3)
654
655
#define LETIMER0_OUT0_PA0 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x0)
656
#define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1)
657
#define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2)
658
#define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3)
659
#define LETIMER0_OUT0_PA4 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x4)
660
#define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5)
661
#define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6)
662
#define LETIMER0_OUT0_PA7 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x7)
663
#define LETIMER0_OUT0_PA8 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x8)
664
#define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0)
665
#define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1)
666
#define LETIMER0_OUT0_PB2 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x2)
667
#define LETIMER0_OUT0_PB3 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x3)
668
#define LETIMER0_OUT0_PB4 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x4)
669
#define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x0)
670
#define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1)
671
#define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2)
672
#define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3)
673
#define LETIMER0_OUT1_PA4 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x4)
674
#define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5)
675
#define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6)
676
#define LETIMER0_OUT1_PA7 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x7)
677
#define LETIMER0_OUT1_PA8 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x8)
678
#define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0)
679
#define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1)
680
#define LETIMER0_OUT1_PB2 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x2)
681
#define LETIMER0_OUT1_PB3 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x3)
682
#define LETIMER0_OUT1_PB4 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x4)
683
684
#define MODEM_ANT0_PA0 SILABS_DBUS_MODEM_ANT0(0x0, 0x0)
685
#define MODEM_ANT0_PA1 SILABS_DBUS_MODEM_ANT0(0x0, 0x1)
686
#define MODEM_ANT0_PA2 SILABS_DBUS_MODEM_ANT0(0x0, 0x2)
687
#define MODEM_ANT0_PA3 SILABS_DBUS_MODEM_ANT0(0x0, 0x3)
688
#define MODEM_ANT0_PA4 SILABS_DBUS_MODEM_ANT0(0x0, 0x4)
689
#define MODEM_ANT0_PA5 SILABS_DBUS_MODEM_ANT0(0x0, 0x5)
690
#define MODEM_ANT0_PA6 SILABS_DBUS_MODEM_ANT0(0x0, 0x6)
691
#define MODEM_ANT0_PA7 SILABS_DBUS_MODEM_ANT0(0x0, 0x7)
692
#define MODEM_ANT0_PA8 SILABS_DBUS_MODEM_ANT0(0x0, 0x8)
693
#define MODEM_ANT0_PB0 SILABS_DBUS_MODEM_ANT0(0x1, 0x0)
694
#define MODEM_ANT0_PB1 SILABS_DBUS_MODEM_ANT0(0x1, 0x1)
695
#define MODEM_ANT0_PB2 SILABS_DBUS_MODEM_ANT0(0x1, 0x2)
696
#define MODEM_ANT0_PB3 SILABS_DBUS_MODEM_ANT0(0x1, 0x3)
697
#define MODEM_ANT0_PB4 SILABS_DBUS_MODEM_ANT0(0x1, 0x4)
698
#define MODEM_ANT0_PC0 SILABS_DBUS_MODEM_ANT0(0x2, 0x0)
699
#define MODEM_ANT0_PC1 SILABS_DBUS_MODEM_ANT0(0x2, 0x1)
700
#define MODEM_ANT0_PC2 SILABS_DBUS_MODEM_ANT0(0x2, 0x2)
701
#define MODEM_ANT0_PC3 SILABS_DBUS_MODEM_ANT0(0x2, 0x3)
702
#define MODEM_ANT0_PC4 SILABS_DBUS_MODEM_ANT0(0x2, 0x4)
703
#define MODEM_ANT0_PC5 SILABS_DBUS_MODEM_ANT0(0x2, 0x5)
704
#define MODEM_ANT0_PC6 SILABS_DBUS_MODEM_ANT0(0x2, 0x6)
705
#define MODEM_ANT0_PC7 SILABS_DBUS_MODEM_ANT0(0x2, 0x7)
706
#define MODEM_ANT0_PD0 SILABS_DBUS_MODEM_ANT0(0x3, 0x0)
707
#define MODEM_ANT0_PD1 SILABS_DBUS_MODEM_ANT0(0x3, 0x1)
708
#define MODEM_ANT0_PD2 SILABS_DBUS_MODEM_ANT0(0x3, 0x2)
709
#define MODEM_ANT0_PD3 SILABS_DBUS_MODEM_ANT0(0x3, 0x3)
710
#define MODEM_ANT1_PA0 SILABS_DBUS_MODEM_ANT1(0x0, 0x0)
711
#define MODEM_ANT1_PA1 SILABS_DBUS_MODEM_ANT1(0x0, 0x1)
712
#define MODEM_ANT1_PA2 SILABS_DBUS_MODEM_ANT1(0x0, 0x2)
713
#define MODEM_ANT1_PA3 SILABS_DBUS_MODEM_ANT1(0x0, 0x3)
714
#define MODEM_ANT1_PA4 SILABS_DBUS_MODEM_ANT1(0x0, 0x4)
715
#define MODEM_ANT1_PA5 SILABS_DBUS_MODEM_ANT1(0x0, 0x5)
716
#define MODEM_ANT1_PA6 SILABS_DBUS_MODEM_ANT1(0x0, 0x6)
717
#define MODEM_ANT1_PA7 SILABS_DBUS_MODEM_ANT1(0x0, 0x7)
718
#define MODEM_ANT1_PA8 SILABS_DBUS_MODEM_ANT1(0x0, 0x8)
719
#define MODEM_ANT1_PB0 SILABS_DBUS_MODEM_ANT1(0x1, 0x0)
720
#define MODEM_ANT1_PB1 SILABS_DBUS_MODEM_ANT1(0x1, 0x1)
721
#define MODEM_ANT1_PB2 SILABS_DBUS_MODEM_ANT1(0x1, 0x2)
722
#define MODEM_ANT1_PB3 SILABS_DBUS_MODEM_ANT1(0x1, 0x3)
723
#define MODEM_ANT1_PB4 SILABS_DBUS_MODEM_ANT1(0x1, 0x4)
724
#define MODEM_ANT1_PC0 SILABS_DBUS_MODEM_ANT1(0x2, 0x0)
725
#define MODEM_ANT1_PC1 SILABS_DBUS_MODEM_ANT1(0x2, 0x1)
726
#define MODEM_ANT1_PC2 SILABS_DBUS_MODEM_ANT1(0x2, 0x2)
727
#define MODEM_ANT1_PC3 SILABS_DBUS_MODEM_ANT1(0x2, 0x3)
728
#define MODEM_ANT1_PC4 SILABS_DBUS_MODEM_ANT1(0x2, 0x4)
729
#define MODEM_ANT1_PC5 SILABS_DBUS_MODEM_ANT1(0x2, 0x5)
730
#define MODEM_ANT1_PC6 SILABS_DBUS_MODEM_ANT1(0x2, 0x6)
731
#define MODEM_ANT1_PC7 SILABS_DBUS_MODEM_ANT1(0x2, 0x7)
732
#define MODEM_ANT1_PD0 SILABS_DBUS_MODEM_ANT1(0x3, 0x0)
733
#define MODEM_ANT1_PD1 SILABS_DBUS_MODEM_ANT1(0x3, 0x1)
734
#define MODEM_ANT1_PD2 SILABS_DBUS_MODEM_ANT1(0x3, 0x2)
735
#define MODEM_ANT1_PD3 SILABS_DBUS_MODEM_ANT1(0x3, 0x3)
736
#define MODEM_ANTROLLOVER_PC0 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x0)
737
#define MODEM_ANTROLLOVER_PC1 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x1)
738
#define MODEM_ANTROLLOVER_PC2 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x2)
739
#define MODEM_ANTROLLOVER_PC3 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x3)
740
#define MODEM_ANTROLLOVER_PC4 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x4)
741
#define MODEM_ANTROLLOVER_PC5 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x5)
742
#define MODEM_ANTROLLOVER_PC6 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x6)
743
#define MODEM_ANTROLLOVER_PC7 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x7)
744
#define MODEM_ANTROLLOVER_PD0 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x0)
745
#define MODEM_ANTROLLOVER_PD1 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x1)
746
#define MODEM_ANTROLLOVER_PD2 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x2)
747
#define MODEM_ANTROLLOVER_PD3 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x3)
748
#define MODEM_ANTRR0_PC0 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x0)
749
#define MODEM_ANTRR0_PC1 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x1)
750
#define MODEM_ANTRR0_PC2 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x2)
751
#define MODEM_ANTRR0_PC3 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x3)
752
#define MODEM_ANTRR0_PC4 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x4)
753
#define MODEM_ANTRR0_PC5 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x5)
754
#define MODEM_ANTRR0_PC6 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x6)
755
#define MODEM_ANTRR0_PC7 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x7)
756
#define MODEM_ANTRR0_PD0 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x0)
757
#define MODEM_ANTRR0_PD1 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x1)
758
#define MODEM_ANTRR0_PD2 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x2)
759
#define MODEM_ANTRR0_PD3 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x3)
760
#define MODEM_ANTRR1_PC0 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x0)
761
#define MODEM_ANTRR1_PC1 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x1)
762
#define MODEM_ANTRR1_PC2 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x2)
763
#define MODEM_ANTRR1_PC3 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x3)
764
#define MODEM_ANTRR1_PC4 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x4)
765
#define MODEM_ANTRR1_PC5 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x5)
766
#define MODEM_ANTRR1_PC6 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x6)
767
#define MODEM_ANTRR1_PC7 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x7)
768
#define MODEM_ANTRR1_PD0 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x0)
769
#define MODEM_ANTRR1_PD1 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x1)
770
#define MODEM_ANTRR1_PD2 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x2)
771
#define MODEM_ANTRR1_PD3 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x3)
772
#define MODEM_ANTRR2_PC0 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x0)
773
#define MODEM_ANTRR2_PC1 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x1)
774
#define MODEM_ANTRR2_PC2 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x2)
775
#define MODEM_ANTRR2_PC3 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x3)
776
#define MODEM_ANTRR2_PC4 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x4)
777
#define MODEM_ANTRR2_PC5 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x5)
778
#define MODEM_ANTRR2_PC6 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x6)
779
#define MODEM_ANTRR2_PC7 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x7)
780
#define MODEM_ANTRR2_PD0 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x0)
781
#define MODEM_ANTRR2_PD1 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x1)
782
#define MODEM_ANTRR2_PD2 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x2)
783
#define MODEM_ANTRR2_PD3 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x3)
784
#define MODEM_ANTRR3_PC0 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x0)
785
#define MODEM_ANTRR3_PC1 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x1)
786
#define MODEM_ANTRR3_PC2 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x2)
787
#define MODEM_ANTRR3_PC3 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x3)
788
#define MODEM_ANTRR3_PC4 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x4)
789
#define MODEM_ANTRR3_PC5 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x5)
790
#define MODEM_ANTRR3_PC6 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x6)
791
#define MODEM_ANTRR3_PC7 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x7)
792
#define MODEM_ANTRR3_PD0 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x0)
793
#define MODEM_ANTRR3_PD1 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x1)
794
#define MODEM_ANTRR3_PD2 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x2)
795
#define MODEM_ANTRR3_PD3 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x3)
796
#define MODEM_ANTRR4_PC0 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x0)
797
#define MODEM_ANTRR4_PC1 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x1)
798
#define MODEM_ANTRR4_PC2 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x2)
799
#define MODEM_ANTRR4_PC3 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x3)
800
#define MODEM_ANTRR4_PC4 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x4)
801
#define MODEM_ANTRR4_PC5 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x5)
802
#define MODEM_ANTRR4_PC6 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x6)
803
#define MODEM_ANTRR4_PC7 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x7)
804
#define MODEM_ANTRR4_PD0 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x0)
805
#define MODEM_ANTRR4_PD1 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x1)
806
#define MODEM_ANTRR4_PD2 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x2)
807
#define MODEM_ANTRR4_PD3 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x3)
808
#define MODEM_ANTRR5_PC0 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x0)
809
#define MODEM_ANTRR5_PC1 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x1)
810
#define MODEM_ANTRR5_PC2 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x2)
811
#define MODEM_ANTRR5_PC3 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x3)
812
#define MODEM_ANTRR5_PC4 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x4)
813
#define MODEM_ANTRR5_PC5 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x5)
814
#define MODEM_ANTRR5_PC6 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x6)
815
#define MODEM_ANTRR5_PC7 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x7)
816
#define MODEM_ANTRR5_PD0 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x0)
817
#define MODEM_ANTRR5_PD1 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x1)
818
#define MODEM_ANTRR5_PD2 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x2)
819
#define MODEM_ANTRR5_PD3 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x3)
820
#define MODEM_ANTSWEN_PC0 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x0)
821
#define MODEM_ANTSWEN_PC1 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x1)
822
#define MODEM_ANTSWEN_PC2 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x2)
823
#define MODEM_ANTSWEN_PC3 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x3)
824
#define MODEM_ANTSWEN_PC4 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x4)
825
#define MODEM_ANTSWEN_PC5 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x5)
826
#define MODEM_ANTSWEN_PC6 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x6)
827
#define MODEM_ANTSWEN_PC7 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x7)
828
#define MODEM_ANTSWEN_PD0 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x0)
829
#define MODEM_ANTSWEN_PD1 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x1)
830
#define MODEM_ANTSWEN_PD2 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x2)
831
#define MODEM_ANTSWEN_PD3 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x3)
832
#define MODEM_ANTSWUS_PC0 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x0)
833
#define MODEM_ANTSWUS_PC1 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x1)
834
#define MODEM_ANTSWUS_PC2 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x2)
835
#define MODEM_ANTSWUS_PC3 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x3)
836
#define MODEM_ANTSWUS_PC4 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x4)
837
#define MODEM_ANTSWUS_PC5 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x5)
838
#define MODEM_ANTSWUS_PC6 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x6)
839
#define MODEM_ANTSWUS_PC7 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x7)
840
#define MODEM_ANTSWUS_PD0 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x0)
841
#define MODEM_ANTSWUS_PD1 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x1)
842
#define MODEM_ANTSWUS_PD2 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x2)
843
#define MODEM_ANTSWUS_PD3 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x3)
844
#define MODEM_ANTTRIG_PC0 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x0)
845
#define MODEM_ANTTRIG_PC1 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x1)
846
#define MODEM_ANTTRIG_PC2 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x2)
847
#define MODEM_ANTTRIG_PC3 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x3)
848
#define MODEM_ANTTRIG_PC4 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x4)
849
#define MODEM_ANTTRIG_PC5 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x5)
850
#define MODEM_ANTTRIG_PC6 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x6)
851
#define MODEM_ANTTRIG_PC7 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x7)
852
#define MODEM_ANTTRIG_PD0 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x0)
853
#define MODEM_ANTTRIG_PD1 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x1)
854
#define MODEM_ANTTRIG_PD2 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x2)
855
#define MODEM_ANTTRIG_PD3 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x3)
856
#define MODEM_ANTTRIGSTOP_PC0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x0)
857
#define MODEM_ANTTRIGSTOP_PC1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x1)
858
#define MODEM_ANTTRIGSTOP_PC2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x2)
859
#define MODEM_ANTTRIGSTOP_PC3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x3)
860
#define MODEM_ANTTRIGSTOP_PC4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x4)
861
#define MODEM_ANTTRIGSTOP_PC5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x5)
862
#define MODEM_ANTTRIGSTOP_PC6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x6)
863
#define MODEM_ANTTRIGSTOP_PC7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x7)
864
#define MODEM_ANTTRIGSTOP_PD0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x0)
865
#define MODEM_ANTTRIGSTOP_PD1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x1)
866
#define MODEM_ANTTRIGSTOP_PD2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x2)
867
#define MODEM_ANTTRIGSTOP_PD3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x3)
868
#define MODEM_DCLK_PA0 SILABS_DBUS_MODEM_DCLK(0x0, 0x0)
869
#define MODEM_DCLK_PA1 SILABS_DBUS_MODEM_DCLK(0x0, 0x1)
870
#define MODEM_DCLK_PA2 SILABS_DBUS_MODEM_DCLK(0x0, 0x2)
871
#define MODEM_DCLK_PA3 SILABS_DBUS_MODEM_DCLK(0x0, 0x3)
872
#define MODEM_DCLK_PA4 SILABS_DBUS_MODEM_DCLK(0x0, 0x4)
873
#define MODEM_DCLK_PA5 SILABS_DBUS_MODEM_DCLK(0x0, 0x5)
874
#define MODEM_DCLK_PA6 SILABS_DBUS_MODEM_DCLK(0x0, 0x6)
875
#define MODEM_DCLK_PA7 SILABS_DBUS_MODEM_DCLK(0x0, 0x7)
876
#define MODEM_DCLK_PA8 SILABS_DBUS_MODEM_DCLK(0x0, 0x8)
877
#define MODEM_DCLK_PB0 SILABS_DBUS_MODEM_DCLK(0x1, 0x0)
878
#define MODEM_DCLK_PB1 SILABS_DBUS_MODEM_DCLK(0x1, 0x1)
879
#define MODEM_DCLK_PB2 SILABS_DBUS_MODEM_DCLK(0x1, 0x2)
880
#define MODEM_DCLK_PB3 SILABS_DBUS_MODEM_DCLK(0x1, 0x3)
881
#define MODEM_DCLK_PB4 SILABS_DBUS_MODEM_DCLK(0x1, 0x4)
882
#define MODEM_DOUT_PA0 SILABS_DBUS_MODEM_DOUT(0x0, 0x0)
883
#define MODEM_DOUT_PA1 SILABS_DBUS_MODEM_DOUT(0x0, 0x1)
884
#define MODEM_DOUT_PA2 SILABS_DBUS_MODEM_DOUT(0x0, 0x2)
885
#define MODEM_DOUT_PA3 SILABS_DBUS_MODEM_DOUT(0x0, 0x3)
886
#define MODEM_DOUT_PA4 SILABS_DBUS_MODEM_DOUT(0x0, 0x4)
887
#define MODEM_DOUT_PA5 SILABS_DBUS_MODEM_DOUT(0x0, 0x5)
888
#define MODEM_DOUT_PA6 SILABS_DBUS_MODEM_DOUT(0x0, 0x6)
889
#define MODEM_DOUT_PA7 SILABS_DBUS_MODEM_DOUT(0x0, 0x7)
890
#define MODEM_DOUT_PA8 SILABS_DBUS_MODEM_DOUT(0x0, 0x8)
891
#define MODEM_DOUT_PB0 SILABS_DBUS_MODEM_DOUT(0x1, 0x0)
892
#define MODEM_DOUT_PB1 SILABS_DBUS_MODEM_DOUT(0x1, 0x1)
893
#define MODEM_DOUT_PB2 SILABS_DBUS_MODEM_DOUT(0x1, 0x2)
894
#define MODEM_DOUT_PB3 SILABS_DBUS_MODEM_DOUT(0x1, 0x3)
895
#define MODEM_DOUT_PB4 SILABS_DBUS_MODEM_DOUT(0x1, 0x4)
896
#define MODEM_DIN_PA0 SILABS_DBUS_MODEM_DIN(0x0, 0x0)
897
#define MODEM_DIN_PA1 SILABS_DBUS_MODEM_DIN(0x0, 0x1)
898
#define MODEM_DIN_PA2 SILABS_DBUS_MODEM_DIN(0x0, 0x2)
899
#define MODEM_DIN_PA3 SILABS_DBUS_MODEM_DIN(0x0, 0x3)
900
#define MODEM_DIN_PA4 SILABS_DBUS_MODEM_DIN(0x0, 0x4)
901
#define MODEM_DIN_PA5 SILABS_DBUS_MODEM_DIN(0x0, 0x5)
902
#define MODEM_DIN_PA6 SILABS_DBUS_MODEM_DIN(0x0, 0x6)
903
#define MODEM_DIN_PA7 SILABS_DBUS_MODEM_DIN(0x0, 0x7)
904
#define MODEM_DIN_PA8 SILABS_DBUS_MODEM_DIN(0x0, 0x8)
905
#define MODEM_DIN_PB0 SILABS_DBUS_MODEM_DIN(0x1, 0x0)
906
#define MODEM_DIN_PB1 SILABS_DBUS_MODEM_DIN(0x1, 0x1)
907
#define MODEM_DIN_PB2 SILABS_DBUS_MODEM_DIN(0x1, 0x2)
908
#define MODEM_DIN_PB3 SILABS_DBUS_MODEM_DIN(0x1, 0x3)
909
#define MODEM_DIN_PB4 SILABS_DBUS_MODEM_DIN(0x1, 0x4)
910
911
#define PDM_CLK_PA0 SILABS_DBUS_PDM_CLK(0x0, 0x0)
912
#define PDM_CLK_PA1 SILABS_DBUS_PDM_CLK(0x0, 0x1)
913
#define PDM_CLK_PA2 SILABS_DBUS_PDM_CLK(0x0, 0x2)
914
#define PDM_CLK_PA3 SILABS_DBUS_PDM_CLK(0x0, 0x3)
915
#define PDM_CLK_PA4 SILABS_DBUS_PDM_CLK(0x0, 0x4)
916
#define PDM_CLK_PA5 SILABS_DBUS_PDM_CLK(0x0, 0x5)
917
#define PDM_CLK_PA6 SILABS_DBUS_PDM_CLK(0x0, 0x6)
918
#define PDM_CLK_PA7 SILABS_DBUS_PDM_CLK(0x0, 0x7)
919
#define PDM_CLK_PA8 SILABS_DBUS_PDM_CLK(0x0, 0x8)
920
#define PDM_CLK_PB0 SILABS_DBUS_PDM_CLK(0x1, 0x0)
921
#define PDM_CLK_PB1 SILABS_DBUS_PDM_CLK(0x1, 0x1)
922
#define PDM_CLK_PB2 SILABS_DBUS_PDM_CLK(0x1, 0x2)
923
#define PDM_CLK_PB3 SILABS_DBUS_PDM_CLK(0x1, 0x3)
924
#define PDM_CLK_PB4 SILABS_DBUS_PDM_CLK(0x1, 0x4)
925
#define PDM_CLK_PC0 SILABS_DBUS_PDM_CLK(0x2, 0x0)
926
#define PDM_CLK_PC1 SILABS_DBUS_PDM_CLK(0x2, 0x1)
927
#define PDM_CLK_PC2 SILABS_DBUS_PDM_CLK(0x2, 0x2)
928
#define PDM_CLK_PC3 SILABS_DBUS_PDM_CLK(0x2, 0x3)
929
#define PDM_CLK_PC4 SILABS_DBUS_PDM_CLK(0x2, 0x4)
930
#define PDM_CLK_PC5 SILABS_DBUS_PDM_CLK(0x2, 0x5)
931
#define PDM_CLK_PC6 SILABS_DBUS_PDM_CLK(0x2, 0x6)
932
#define PDM_CLK_PC7 SILABS_DBUS_PDM_CLK(0x2, 0x7)
933
#define PDM_CLK_PD0 SILABS_DBUS_PDM_CLK(0x3, 0x0)
934
#define PDM_CLK_PD1 SILABS_DBUS_PDM_CLK(0x3, 0x1)
935
#define PDM_CLK_PD2 SILABS_DBUS_PDM_CLK(0x3, 0x2)
936
#define PDM_CLK_PD3 SILABS_DBUS_PDM_CLK(0x3, 0x3)
937
#define PDM_DAT0_PA0 SILABS_DBUS_PDM_DAT0(0x0, 0x0)
938
#define PDM_DAT0_PA1 SILABS_DBUS_PDM_DAT0(0x0, 0x1)
939
#define PDM_DAT0_PA2 SILABS_DBUS_PDM_DAT0(0x0, 0x2)
940
#define PDM_DAT0_PA3 SILABS_DBUS_PDM_DAT0(0x0, 0x3)
941
#define PDM_DAT0_PA4 SILABS_DBUS_PDM_DAT0(0x0, 0x4)
942
#define PDM_DAT0_PA5 SILABS_DBUS_PDM_DAT0(0x0, 0x5)
943
#define PDM_DAT0_PA6 SILABS_DBUS_PDM_DAT0(0x0, 0x6)
944
#define PDM_DAT0_PA7 SILABS_DBUS_PDM_DAT0(0x0, 0x7)
945
#define PDM_DAT0_PA8 SILABS_DBUS_PDM_DAT0(0x0, 0x8)
946
#define PDM_DAT0_PB0 SILABS_DBUS_PDM_DAT0(0x1, 0x0)
947
#define PDM_DAT0_PB1 SILABS_DBUS_PDM_DAT0(0x1, 0x1)
948
#define PDM_DAT0_PB2 SILABS_DBUS_PDM_DAT0(0x1, 0x2)
949
#define PDM_DAT0_PB3 SILABS_DBUS_PDM_DAT0(0x1, 0x3)
950
#define PDM_DAT0_PB4 SILABS_DBUS_PDM_DAT0(0x1, 0x4)
951
#define PDM_DAT0_PC0 SILABS_DBUS_PDM_DAT0(0x2, 0x0)
952
#define PDM_DAT0_PC1 SILABS_DBUS_PDM_DAT0(0x2, 0x1)
953
#define PDM_DAT0_PC2 SILABS_DBUS_PDM_DAT0(0x2, 0x2)
954
#define PDM_DAT0_PC3 SILABS_DBUS_PDM_DAT0(0x2, 0x3)
955
#define PDM_DAT0_PC4 SILABS_DBUS_PDM_DAT0(0x2, 0x4)
956
#define PDM_DAT0_PC5 SILABS_DBUS_PDM_DAT0(0x2, 0x5)
957
#define PDM_DAT0_PC6 SILABS_DBUS_PDM_DAT0(0x2, 0x6)
958
#define PDM_DAT0_PC7 SILABS_DBUS_PDM_DAT0(0x2, 0x7)
959
#define PDM_DAT0_PD0 SILABS_DBUS_PDM_DAT0(0x3, 0x0)
960
#define PDM_DAT0_PD1 SILABS_DBUS_PDM_DAT0(0x3, 0x1)
961
#define PDM_DAT0_PD2 SILABS_DBUS_PDM_DAT0(0x3, 0x2)
962
#define PDM_DAT0_PD3 SILABS_DBUS_PDM_DAT0(0x3, 0x3)
963
#define PDM_DAT1_PA0 SILABS_DBUS_PDM_DAT1(0x0, 0x0)
964
#define PDM_DAT1_PA1 SILABS_DBUS_PDM_DAT1(0x0, 0x1)
965
#define PDM_DAT1_PA2 SILABS_DBUS_PDM_DAT1(0x0, 0x2)
966
#define PDM_DAT1_PA3 SILABS_DBUS_PDM_DAT1(0x0, 0x3)
967
#define PDM_DAT1_PA4 SILABS_DBUS_PDM_DAT1(0x0, 0x4)
968
#define PDM_DAT1_PA5 SILABS_DBUS_PDM_DAT1(0x0, 0x5)
969
#define PDM_DAT1_PA6 SILABS_DBUS_PDM_DAT1(0x0, 0x6)
970
#define PDM_DAT1_PA7 SILABS_DBUS_PDM_DAT1(0x0, 0x7)
971
#define PDM_DAT1_PA8 SILABS_DBUS_PDM_DAT1(0x0, 0x8)
972
#define PDM_DAT1_PB0 SILABS_DBUS_PDM_DAT1(0x1, 0x0)
973
#define PDM_DAT1_PB1 SILABS_DBUS_PDM_DAT1(0x1, 0x1)
974
#define PDM_DAT1_PB2 SILABS_DBUS_PDM_DAT1(0x1, 0x2)
975
#define PDM_DAT1_PB3 SILABS_DBUS_PDM_DAT1(0x1, 0x3)
976
#define PDM_DAT1_PB4 SILABS_DBUS_PDM_DAT1(0x1, 0x4)
977
#define PDM_DAT1_PC0 SILABS_DBUS_PDM_DAT1(0x2, 0x0)
978
#define PDM_DAT1_PC1 SILABS_DBUS_PDM_DAT1(0x2, 0x1)
979
#define PDM_DAT1_PC2 SILABS_DBUS_PDM_DAT1(0x2, 0x2)
980
#define PDM_DAT1_PC3 SILABS_DBUS_PDM_DAT1(0x2, 0x3)
981
#define PDM_DAT1_PC4 SILABS_DBUS_PDM_DAT1(0x2, 0x4)
982
#define PDM_DAT1_PC5 SILABS_DBUS_PDM_DAT1(0x2, 0x5)
983
#define PDM_DAT1_PC6 SILABS_DBUS_PDM_DAT1(0x2, 0x6)
984
#define PDM_DAT1_PC7 SILABS_DBUS_PDM_DAT1(0x2, 0x7)
985
#define PDM_DAT1_PD0 SILABS_DBUS_PDM_DAT1(0x3, 0x0)
986
#define PDM_DAT1_PD1 SILABS_DBUS_PDM_DAT1(0x3, 0x1)
987
#define PDM_DAT1_PD2 SILABS_DBUS_PDM_DAT1(0x3, 0x2)
988
#define PDM_DAT1_PD3 SILABS_DBUS_PDM_DAT1(0x3, 0x3)
989
990
#define PRS0_ASYNCH0_PA0 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x0)
991
#define PRS0_ASYNCH0_PA1 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1)
992
#define PRS0_ASYNCH0_PA2 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2)
993
#define PRS0_ASYNCH0_PA3 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3)
994
#define PRS0_ASYNCH0_PA4 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x4)
995
#define PRS0_ASYNCH0_PA5 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5)
996
#define PRS0_ASYNCH0_PA6 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6)
997
#define PRS0_ASYNCH0_PA7 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x7)
998
#define PRS0_ASYNCH0_PA8 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x8)
999
#define PRS0_ASYNCH0_PB0 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0)
1000
#define PRS0_ASYNCH0_PB1 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1)
1001
#define PRS0_ASYNCH0_PB2 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x2)
1002
#define PRS0_ASYNCH0_PB3 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x3)
1003
#define PRS0_ASYNCH0_PB4 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x4)
1004
#define PRS0_ASYNCH1_PA0 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x0)
1005
#define PRS0_ASYNCH1_PA1 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1)
1006
#define PRS0_ASYNCH1_PA2 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2)
1007
#define PRS0_ASYNCH1_PA3 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3)
1008
#define PRS0_ASYNCH1_PA4 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x4)
1009
#define PRS0_ASYNCH1_PA5 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5)
1010
#define PRS0_ASYNCH1_PA6 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6)
1011
#define PRS0_ASYNCH1_PA7 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x7)
1012
#define PRS0_ASYNCH1_PA8 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x8)
1013
#define PRS0_ASYNCH1_PB0 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0)
1014
#define PRS0_ASYNCH1_PB1 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1)
1015
#define PRS0_ASYNCH1_PB2 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x2)
1016
#define PRS0_ASYNCH1_PB3 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x3)
1017
#define PRS0_ASYNCH1_PB4 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x4)
1018
#define PRS0_ASYNCH2_PA0 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x0)
1019
#define PRS0_ASYNCH2_PA1 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1)
1020
#define PRS0_ASYNCH2_PA2 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2)
1021
#define PRS0_ASYNCH2_PA3 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3)
1022
#define PRS0_ASYNCH2_PA4 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x4)
1023
#define PRS0_ASYNCH2_PA5 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5)
1024
#define PRS0_ASYNCH2_PA6 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6)
1025
#define PRS0_ASYNCH2_PA7 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x7)
1026
#define PRS0_ASYNCH2_PA8 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x8)
1027
#define PRS0_ASYNCH2_PB0 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0)
1028
#define PRS0_ASYNCH2_PB1 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1)
1029
#define PRS0_ASYNCH2_PB2 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x2)
1030
#define PRS0_ASYNCH2_PB3 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x3)
1031
#define PRS0_ASYNCH2_PB4 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x4)
1032
#define PRS0_ASYNCH3_PA0 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x0)
1033
#define PRS0_ASYNCH3_PA1 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1)
1034
#define PRS0_ASYNCH3_PA2 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2)
1035
#define PRS0_ASYNCH3_PA3 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3)
1036
#define PRS0_ASYNCH3_PA4 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x4)
1037
#define PRS0_ASYNCH3_PA5 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5)
1038
#define PRS0_ASYNCH3_PA6 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6)
1039
#define PRS0_ASYNCH3_PA7 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x7)
1040
#define PRS0_ASYNCH3_PA8 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x8)
1041
#define PRS0_ASYNCH3_PB0 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0)
1042
#define PRS0_ASYNCH3_PB1 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1)
1043
#define PRS0_ASYNCH3_PB2 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x2)
1044
#define PRS0_ASYNCH3_PB3 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x3)
1045
#define PRS0_ASYNCH3_PB4 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x4)
1046
#define PRS0_ASYNCH4_PA0 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x0)
1047
#define PRS0_ASYNCH4_PA1 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1)
1048
#define PRS0_ASYNCH4_PA2 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2)
1049
#define PRS0_ASYNCH4_PA3 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3)
1050
#define PRS0_ASYNCH4_PA4 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x4)
1051
#define PRS0_ASYNCH4_PA5 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5)
1052
#define PRS0_ASYNCH4_PA6 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6)
1053
#define PRS0_ASYNCH4_PA7 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x7)
1054
#define PRS0_ASYNCH4_PA8 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x8)
1055
#define PRS0_ASYNCH4_PB0 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0)
1056
#define PRS0_ASYNCH4_PB1 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1)
1057
#define PRS0_ASYNCH4_PB2 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x2)
1058
#define PRS0_ASYNCH4_PB3 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x3)
1059
#define PRS0_ASYNCH4_PB4 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x4)
1060
#define PRS0_ASYNCH5_PA0 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x0)
1061
#define PRS0_ASYNCH5_PA1 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1)
1062
#define PRS0_ASYNCH5_PA2 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2)
1063
#define PRS0_ASYNCH5_PA3 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3)
1064
#define PRS0_ASYNCH5_PA4 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x4)
1065
#define PRS0_ASYNCH5_PA5 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5)
1066
#define PRS0_ASYNCH5_PA6 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6)
1067
#define PRS0_ASYNCH5_PA7 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x7)
1068
#define PRS0_ASYNCH5_PA8 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x8)
1069
#define PRS0_ASYNCH5_PB0 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0)
1070
#define PRS0_ASYNCH5_PB1 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1)
1071
#define PRS0_ASYNCH5_PB2 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x2)
1072
#define PRS0_ASYNCH5_PB3 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x3)
1073
#define PRS0_ASYNCH5_PB4 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x4)
1074
#define PRS0_ASYNCH6_PC0 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0)
1075
#define PRS0_ASYNCH6_PC1 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1)
1076
#define PRS0_ASYNCH6_PC2 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2)
1077
#define PRS0_ASYNCH6_PC3 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3)
1078
#define PRS0_ASYNCH6_PC4 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4)
1079
#define PRS0_ASYNCH6_PC5 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5)
1080
#define PRS0_ASYNCH6_PC6 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x6)
1081
#define PRS0_ASYNCH6_PC7 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x7)
1082
#define PRS0_ASYNCH6_PD0 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0)
1083
#define PRS0_ASYNCH6_PD1 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1)
1084
#define PRS0_ASYNCH6_PD2 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2)
1085
#define PRS0_ASYNCH6_PD3 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3)
1086
#define PRS0_ASYNCH7_PC0 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0)
1087
#define PRS0_ASYNCH7_PC1 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1)
1088
#define PRS0_ASYNCH7_PC2 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2)
1089
#define PRS0_ASYNCH7_PC3 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3)
1090
#define PRS0_ASYNCH7_PC4 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4)
1091
#define PRS0_ASYNCH7_PC5 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5)
1092
#define PRS0_ASYNCH7_PC6 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x6)
1093
#define PRS0_ASYNCH7_PC7 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x7)
1094
#define PRS0_ASYNCH7_PD0 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0)
1095
#define PRS0_ASYNCH7_PD1 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1)
1096
#define PRS0_ASYNCH7_PD2 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2)
1097
#define PRS0_ASYNCH7_PD3 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3)
1098
#define PRS0_ASYNCH8_PC0 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0)
1099
#define PRS0_ASYNCH8_PC1 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1)
1100
#define PRS0_ASYNCH8_PC2 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2)
1101
#define PRS0_ASYNCH8_PC3 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3)
1102
#define PRS0_ASYNCH8_PC4 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4)
1103
#define PRS0_ASYNCH8_PC5 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5)
1104
#define PRS0_ASYNCH8_PC6 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x6)
1105
#define PRS0_ASYNCH8_PC7 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x7)
1106
#define PRS0_ASYNCH8_PD0 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0)
1107
#define PRS0_ASYNCH8_PD1 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1)
1108
#define PRS0_ASYNCH8_PD2 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2)
1109
#define PRS0_ASYNCH8_PD3 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3)
1110
#define PRS0_ASYNCH9_PC0 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0)
1111
#define PRS0_ASYNCH9_PC1 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1)
1112
#define PRS0_ASYNCH9_PC2 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2)
1113
#define PRS0_ASYNCH9_PC3 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3)
1114
#define PRS0_ASYNCH9_PC4 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4)
1115
#define PRS0_ASYNCH9_PC5 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5)
1116
#define PRS0_ASYNCH9_PC6 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x6)
1117
#define PRS0_ASYNCH9_PC7 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x7)
1118
#define PRS0_ASYNCH9_PD0 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0)
1119
#define PRS0_ASYNCH9_PD1 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1)
1120
#define PRS0_ASYNCH9_PD2 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2)
1121
#define PRS0_ASYNCH9_PD3 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3)
1122
#define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0)
1123
#define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1)
1124
#define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2)
1125
#define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3)
1126
#define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4)
1127
#define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5)
1128
#define PRS0_ASYNCH10_PC6 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x6)
1129
#define PRS0_ASYNCH10_PC7 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x7)
1130
#define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0)
1131
#define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1)
1132
#define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2)
1133
#define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3)
1134
#define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0)
1135
#define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1)
1136
#define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2)
1137
#define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3)
1138
#define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4)
1139
#define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5)
1140
#define PRS0_ASYNCH11_PC6 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x6)
1141
#define PRS0_ASYNCH11_PC7 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x7)
1142
#define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0)
1143
#define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1)
1144
#define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2)
1145
#define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3)
1146
#define PRS0_SYNCH0_PA0 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x0)
1147
#define PRS0_SYNCH0_PA1 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1)
1148
#define PRS0_SYNCH0_PA2 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2)
1149
#define PRS0_SYNCH0_PA3 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3)
1150
#define PRS0_SYNCH0_PA4 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x4)
1151
#define PRS0_SYNCH0_PA5 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5)
1152
#define PRS0_SYNCH0_PA6 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6)
1153
#define PRS0_SYNCH0_PA7 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x7)
1154
#define PRS0_SYNCH0_PA8 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x8)
1155
#define PRS0_SYNCH0_PB0 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0)
1156
#define PRS0_SYNCH0_PB1 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1)
1157
#define PRS0_SYNCH0_PB2 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x2)
1158
#define PRS0_SYNCH0_PB3 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x3)
1159
#define PRS0_SYNCH0_PB4 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x4)
1160
#define PRS0_SYNCH0_PC0 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0)
1161
#define PRS0_SYNCH0_PC1 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1)
1162
#define PRS0_SYNCH0_PC2 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2)
1163
#define PRS0_SYNCH0_PC3 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3)
1164
#define PRS0_SYNCH0_PC4 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4)
1165
#define PRS0_SYNCH0_PC5 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5)
1166
#define PRS0_SYNCH0_PC6 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x6)
1167
#define PRS0_SYNCH0_PC7 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x7)
1168
#define PRS0_SYNCH0_PD0 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0)
1169
#define PRS0_SYNCH0_PD1 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1)
1170
#define PRS0_SYNCH0_PD2 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2)
1171
#define PRS0_SYNCH0_PD3 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3)
1172
#define PRS0_SYNCH1_PA0 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x0)
1173
#define PRS0_SYNCH1_PA1 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1)
1174
#define PRS0_SYNCH1_PA2 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2)
1175
#define PRS0_SYNCH1_PA3 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3)
1176
#define PRS0_SYNCH1_PA4 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x4)
1177
#define PRS0_SYNCH1_PA5 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5)
1178
#define PRS0_SYNCH1_PA6 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6)
1179
#define PRS0_SYNCH1_PA7 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x7)
1180
#define PRS0_SYNCH1_PA8 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x8)
1181
#define PRS0_SYNCH1_PB0 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0)
1182
#define PRS0_SYNCH1_PB1 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1)
1183
#define PRS0_SYNCH1_PB2 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x2)
1184
#define PRS0_SYNCH1_PB3 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x3)
1185
#define PRS0_SYNCH1_PB4 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x4)
1186
#define PRS0_SYNCH1_PC0 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0)
1187
#define PRS0_SYNCH1_PC1 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1)
1188
#define PRS0_SYNCH1_PC2 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2)
1189
#define PRS0_SYNCH1_PC3 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3)
1190
#define PRS0_SYNCH1_PC4 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4)
1191
#define PRS0_SYNCH1_PC5 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5)
1192
#define PRS0_SYNCH1_PC6 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x6)
1193
#define PRS0_SYNCH1_PC7 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x7)
1194
#define PRS0_SYNCH1_PD0 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0)
1195
#define PRS0_SYNCH1_PD1 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1)
1196
#define PRS0_SYNCH1_PD2 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2)
1197
#define PRS0_SYNCH1_PD3 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3)
1198
#define PRS0_SYNCH2_PA0 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x0)
1199
#define PRS0_SYNCH2_PA1 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1)
1200
#define PRS0_SYNCH2_PA2 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2)
1201
#define PRS0_SYNCH2_PA3 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3)
1202
#define PRS0_SYNCH2_PA4 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x4)
1203
#define PRS0_SYNCH2_PA5 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5)
1204
#define PRS0_SYNCH2_PA6 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6)
1205
#define PRS0_SYNCH2_PA7 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x7)
1206
#define PRS0_SYNCH2_PA8 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x8)
1207
#define PRS0_SYNCH2_PB0 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0)
1208
#define PRS0_SYNCH2_PB1 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1)
1209
#define PRS0_SYNCH2_PB2 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x2)
1210
#define PRS0_SYNCH2_PB3 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x3)
1211
#define PRS0_SYNCH2_PB4 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x4)
1212
#define PRS0_SYNCH2_PC0 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0)
1213
#define PRS0_SYNCH2_PC1 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1)
1214
#define PRS0_SYNCH2_PC2 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2)
1215
#define PRS0_SYNCH2_PC3 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3)
1216
#define PRS0_SYNCH2_PC4 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4)
1217
#define PRS0_SYNCH2_PC5 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5)
1218
#define PRS0_SYNCH2_PC6 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x6)
1219
#define PRS0_SYNCH2_PC7 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x7)
1220
#define PRS0_SYNCH2_PD0 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0)
1221
#define PRS0_SYNCH2_PD1 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1)
1222
#define PRS0_SYNCH2_PD2 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2)
1223
#define PRS0_SYNCH2_PD3 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3)
1224
#define PRS0_SYNCH3_PA0 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x0)
1225
#define PRS0_SYNCH3_PA1 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1)
1226
#define PRS0_SYNCH3_PA2 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2)
1227
#define PRS0_SYNCH3_PA3 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3)
1228
#define PRS0_SYNCH3_PA4 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x4)
1229
#define PRS0_SYNCH3_PA5 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5)
1230
#define PRS0_SYNCH3_PA6 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6)
1231
#define PRS0_SYNCH3_PA7 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x7)
1232
#define PRS0_SYNCH3_PA8 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x8)
1233
#define PRS0_SYNCH3_PB0 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0)
1234
#define PRS0_SYNCH3_PB1 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1)
1235
#define PRS0_SYNCH3_PB2 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x2)
1236
#define PRS0_SYNCH3_PB3 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x3)
1237
#define PRS0_SYNCH3_PB4 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x4)
1238
#define PRS0_SYNCH3_PC0 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0)
1239
#define PRS0_SYNCH3_PC1 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1)
1240
#define PRS0_SYNCH3_PC2 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2)
1241
#define PRS0_SYNCH3_PC3 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3)
1242
#define PRS0_SYNCH3_PC4 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4)
1243
#define PRS0_SYNCH3_PC5 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5)
1244
#define PRS0_SYNCH3_PC6 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x6)
1245
#define PRS0_SYNCH3_PC7 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x7)
1246
#define PRS0_SYNCH3_PD0 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0)
1247
#define PRS0_SYNCH3_PD1 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1)
1248
#define PRS0_SYNCH3_PD2 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2)
1249
#define PRS0_SYNCH3_PD3 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3)
1250
1251
#define TIMER0_CC0_PA0 SILABS_DBUS_TIMER0_CC0(0x0, 0x0)
1252
#define TIMER0_CC0_PA1 SILABS_DBUS_TIMER0_CC0(0x0, 0x1)
1253
#define TIMER0_CC0_PA2 SILABS_DBUS_TIMER0_CC0(0x0, 0x2)
1254
#define TIMER0_CC0_PA3 SILABS_DBUS_TIMER0_CC0(0x0, 0x3)
1255
#define TIMER0_CC0_PA4 SILABS_DBUS_TIMER0_CC0(0x0, 0x4)
1256
#define TIMER0_CC0_PA5 SILABS_DBUS_TIMER0_CC0(0x0, 0x5)
1257
#define TIMER0_CC0_PA6 SILABS_DBUS_TIMER0_CC0(0x0, 0x6)
1258
#define TIMER0_CC0_PA7 SILABS_DBUS_TIMER0_CC0(0x0, 0x7)
1259
#define TIMER0_CC0_PA8 SILABS_DBUS_TIMER0_CC0(0x0, 0x8)
1260
#define TIMER0_CC0_PB0 SILABS_DBUS_TIMER0_CC0(0x1, 0x0)
1261
#define TIMER0_CC0_PB1 SILABS_DBUS_TIMER0_CC0(0x1, 0x1)
1262
#define TIMER0_CC0_PB2 SILABS_DBUS_TIMER0_CC0(0x1, 0x2)
1263
#define TIMER0_CC0_PB3 SILABS_DBUS_TIMER0_CC0(0x1, 0x3)
1264
#define TIMER0_CC0_PB4 SILABS_DBUS_TIMER0_CC0(0x1, 0x4)
1265
#define TIMER0_CC0_PC0 SILABS_DBUS_TIMER0_CC0(0x2, 0x0)
1266
#define TIMER0_CC0_PC1 SILABS_DBUS_TIMER0_CC0(0x2, 0x1)
1267
#define TIMER0_CC0_PC2 SILABS_DBUS_TIMER0_CC0(0x2, 0x2)
1268
#define TIMER0_CC0_PC3 SILABS_DBUS_TIMER0_CC0(0x2, 0x3)
1269
#define TIMER0_CC0_PC4 SILABS_DBUS_TIMER0_CC0(0x2, 0x4)
1270
#define TIMER0_CC0_PC5 SILABS_DBUS_TIMER0_CC0(0x2, 0x5)
1271
#define TIMER0_CC0_PC6 SILABS_DBUS_TIMER0_CC0(0x2, 0x6)
1272
#define TIMER0_CC0_PC7 SILABS_DBUS_TIMER0_CC0(0x2, 0x7)
1273
#define TIMER0_CC0_PD0 SILABS_DBUS_TIMER0_CC0(0x3, 0x0)
1274
#define TIMER0_CC0_PD1 SILABS_DBUS_TIMER0_CC0(0x3, 0x1)
1275
#define TIMER0_CC0_PD2 SILABS_DBUS_TIMER0_CC0(0x3, 0x2)
1276
#define TIMER0_CC0_PD3 SILABS_DBUS_TIMER0_CC0(0x3, 0x3)
1277
#define TIMER0_CC1_PA0 SILABS_DBUS_TIMER0_CC1(0x0, 0x0)
1278
#define TIMER0_CC1_PA1 SILABS_DBUS_TIMER0_CC1(0x0, 0x1)
1279
#define TIMER0_CC1_PA2 SILABS_DBUS_TIMER0_CC1(0x0, 0x2)
1280
#define TIMER0_CC1_PA3 SILABS_DBUS_TIMER0_CC1(0x0, 0x3)
1281
#define TIMER0_CC1_PA4 SILABS_DBUS_TIMER0_CC1(0x0, 0x4)
1282
#define TIMER0_CC1_PA5 SILABS_DBUS_TIMER0_CC1(0x0, 0x5)
1283
#define TIMER0_CC1_PA6 SILABS_DBUS_TIMER0_CC1(0x0, 0x6)
1284
#define TIMER0_CC1_PA7 SILABS_DBUS_TIMER0_CC1(0x0, 0x7)
1285
#define TIMER0_CC1_PA8 SILABS_DBUS_TIMER0_CC1(0x0, 0x8)
1286
#define TIMER0_CC1_PB0 SILABS_DBUS_TIMER0_CC1(0x1, 0x0)
1287
#define TIMER0_CC1_PB1 SILABS_DBUS_TIMER0_CC1(0x1, 0x1)
1288
#define TIMER0_CC1_PB2 SILABS_DBUS_TIMER0_CC1(0x1, 0x2)
1289
#define TIMER0_CC1_PB3 SILABS_DBUS_TIMER0_CC1(0x1, 0x3)
1290
#define TIMER0_CC1_PB4 SILABS_DBUS_TIMER0_CC1(0x1, 0x4)
1291
#define TIMER0_CC1_PC0 SILABS_DBUS_TIMER0_CC1(0x2, 0x0)
1292
#define TIMER0_CC1_PC1 SILABS_DBUS_TIMER0_CC1(0x2, 0x1)
1293
#define TIMER0_CC1_PC2 SILABS_DBUS_TIMER0_CC1(0x2, 0x2)
1294
#define TIMER0_CC1_PC3 SILABS_DBUS_TIMER0_CC1(0x2, 0x3)
1295
#define TIMER0_CC1_PC4 SILABS_DBUS_TIMER0_CC1(0x2, 0x4)
1296
#define TIMER0_CC1_PC5 SILABS_DBUS_TIMER0_CC1(0x2, 0x5)
1297
#define TIMER0_CC1_PC6 SILABS_DBUS_TIMER0_CC1(0x2, 0x6)
1298
#define TIMER0_CC1_PC7 SILABS_DBUS_TIMER0_CC1(0x2, 0x7)
1299
#define TIMER0_CC1_PD0 SILABS_DBUS_TIMER0_CC1(0x3, 0x0)
1300
#define TIMER0_CC1_PD1 SILABS_DBUS_TIMER0_CC1(0x3, 0x1)
1301
#define TIMER0_CC1_PD2 SILABS_DBUS_TIMER0_CC1(0x3, 0x2)
1302
#define TIMER0_CC1_PD3 SILABS_DBUS_TIMER0_CC1(0x3, 0x3)
1303
#define TIMER0_CC2_PA0 SILABS_DBUS_TIMER0_CC2(0x0, 0x0)
1304
#define TIMER0_CC2_PA1 SILABS_DBUS_TIMER0_CC2(0x0, 0x1)
1305
#define TIMER0_CC2_PA2 SILABS_DBUS_TIMER0_CC2(0x0, 0x2)
1306
#define TIMER0_CC2_PA3 SILABS_DBUS_TIMER0_CC2(0x0, 0x3)
1307
#define TIMER0_CC2_PA4 SILABS_DBUS_TIMER0_CC2(0x0, 0x4)
1308
#define TIMER0_CC2_PA5 SILABS_DBUS_TIMER0_CC2(0x0, 0x5)
1309
#define TIMER0_CC2_PA6 SILABS_DBUS_TIMER0_CC2(0x0, 0x6)
1310
#define TIMER0_CC2_PA7 SILABS_DBUS_TIMER0_CC2(0x0, 0x7)
1311
#define TIMER0_CC2_PA8 SILABS_DBUS_TIMER0_CC2(0x0, 0x8)
1312
#define TIMER0_CC2_PB0 SILABS_DBUS_TIMER0_CC2(0x1, 0x0)
1313
#define TIMER0_CC2_PB1 SILABS_DBUS_TIMER0_CC2(0x1, 0x1)
1314
#define TIMER0_CC2_PB2 SILABS_DBUS_TIMER0_CC2(0x1, 0x2)
1315
#define TIMER0_CC2_PB3 SILABS_DBUS_TIMER0_CC2(0x1, 0x3)
1316
#define TIMER0_CC2_PB4 SILABS_DBUS_TIMER0_CC2(0x1, 0x4)
1317
#define TIMER0_CC2_PC0 SILABS_DBUS_TIMER0_CC2(0x2, 0x0)
1318
#define TIMER0_CC2_PC1 SILABS_DBUS_TIMER0_CC2(0x2, 0x1)
1319
#define TIMER0_CC2_PC2 SILABS_DBUS_TIMER0_CC2(0x2, 0x2)
1320
#define TIMER0_CC2_PC3 SILABS_DBUS_TIMER0_CC2(0x2, 0x3)
1321
#define TIMER0_CC2_PC4 SILABS_DBUS_TIMER0_CC2(0x2, 0x4)
1322
#define TIMER0_CC2_PC5 SILABS_DBUS_TIMER0_CC2(0x2, 0x5)
1323
#define TIMER0_CC2_PC6 SILABS_DBUS_TIMER0_CC2(0x2, 0x6)
1324
#define TIMER0_CC2_PC7 SILABS_DBUS_TIMER0_CC2(0x2, 0x7)
1325
#define TIMER0_CC2_PD0 SILABS_DBUS_TIMER0_CC2(0x3, 0x0)
1326
#define TIMER0_CC2_PD1 SILABS_DBUS_TIMER0_CC2(0x3, 0x1)
1327
#define TIMER0_CC2_PD2 SILABS_DBUS_TIMER0_CC2(0x3, 0x2)
1328
#define TIMER0_CC2_PD3 SILABS_DBUS_TIMER0_CC2(0x3, 0x3)
1329
#define TIMER0_CDTI0_PA0 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x0)
1330
#define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1)
1331
#define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2)
1332
#define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3)
1333
#define TIMER0_CDTI0_PA4 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x4)
1334
#define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5)
1335
#define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6)
1336
#define TIMER0_CDTI0_PA7 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x7)
1337
#define TIMER0_CDTI0_PA8 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x8)
1338
#define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0)
1339
#define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1)
1340
#define TIMER0_CDTI0_PB2 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x2)
1341
#define TIMER0_CDTI0_PB3 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x3)
1342
#define TIMER0_CDTI0_PB4 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x4)
1343
#define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0)
1344
#define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1)
1345
#define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2)
1346
#define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3)
1347
#define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4)
1348
#define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5)
1349
#define TIMER0_CDTI0_PC6 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x6)
1350
#define TIMER0_CDTI0_PC7 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x7)
1351
#define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0)
1352
#define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1)
1353
#define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2)
1354
#define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3)
1355
#define TIMER0_CDTI1_PA0 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x0)
1356
#define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1)
1357
#define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2)
1358
#define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3)
1359
#define TIMER0_CDTI1_PA4 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x4)
1360
#define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5)
1361
#define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6)
1362
#define TIMER0_CDTI1_PA7 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x7)
1363
#define TIMER0_CDTI1_PA8 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x8)
1364
#define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0)
1365
#define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1)
1366
#define TIMER0_CDTI1_PB2 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x2)
1367
#define TIMER0_CDTI1_PB3 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x3)
1368
#define TIMER0_CDTI1_PB4 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x4)
1369
#define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0)
1370
#define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1)
1371
#define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2)
1372
#define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3)
1373
#define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4)
1374
#define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5)
1375
#define TIMER0_CDTI1_PC6 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x6)
1376
#define TIMER0_CDTI1_PC7 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x7)
1377
#define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0)
1378
#define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1)
1379
#define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2)
1380
#define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3)
1381
#define TIMER0_CDTI2_PA0 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x0)
1382
#define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1)
1383
#define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2)
1384
#define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3)
1385
#define TIMER0_CDTI2_PA4 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x4)
1386
#define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5)
1387
#define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6)
1388
#define TIMER0_CDTI2_PA7 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x7)
1389
#define TIMER0_CDTI2_PA8 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x8)
1390
#define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0)
1391
#define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1)
1392
#define TIMER0_CDTI2_PB2 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x2)
1393
#define TIMER0_CDTI2_PB3 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x3)
1394
#define TIMER0_CDTI2_PB4 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x4)
1395
#define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0)
1396
#define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1)
1397
#define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2)
1398
#define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3)
1399
#define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4)
1400
#define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5)
1401
#define TIMER0_CDTI2_PC6 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x6)
1402
#define TIMER0_CDTI2_PC7 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x7)
1403
#define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0)
1404
#define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1)
1405
#define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2)
1406
#define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3)
1407
1408
#define TIMER1_CC0_PA0 SILABS_DBUS_TIMER1_CC0(0x0, 0x0)
1409
#define TIMER1_CC0_PA1 SILABS_DBUS_TIMER1_CC0(0x0, 0x1)
1410
#define TIMER1_CC0_PA2 SILABS_DBUS_TIMER1_CC0(0x0, 0x2)
1411
#define TIMER1_CC0_PA3 SILABS_DBUS_TIMER1_CC0(0x0, 0x3)
1412
#define TIMER1_CC0_PA4 SILABS_DBUS_TIMER1_CC0(0x0, 0x4)
1413
#define TIMER1_CC0_PA5 SILABS_DBUS_TIMER1_CC0(0x0, 0x5)
1414
#define TIMER1_CC0_PA6 SILABS_DBUS_TIMER1_CC0(0x0, 0x6)
1415
#define TIMER1_CC0_PA7 SILABS_DBUS_TIMER1_CC0(0x0, 0x7)
1416
#define TIMER1_CC0_PA8 SILABS_DBUS_TIMER1_CC0(0x0, 0x8)
1417
#define TIMER1_CC0_PB0 SILABS_DBUS_TIMER1_CC0(0x1, 0x0)
1418
#define TIMER1_CC0_PB1 SILABS_DBUS_TIMER1_CC0(0x1, 0x1)
1419
#define TIMER1_CC0_PB2 SILABS_DBUS_TIMER1_CC0(0x1, 0x2)
1420
#define TIMER1_CC0_PB3 SILABS_DBUS_TIMER1_CC0(0x1, 0x3)
1421
#define TIMER1_CC0_PB4 SILABS_DBUS_TIMER1_CC0(0x1, 0x4)
1422
#define TIMER1_CC0_PC0 SILABS_DBUS_TIMER1_CC0(0x2, 0x0)
1423
#define TIMER1_CC0_PC1 SILABS_DBUS_TIMER1_CC0(0x2, 0x1)
1424
#define TIMER1_CC0_PC2 SILABS_DBUS_TIMER1_CC0(0x2, 0x2)
1425
#define TIMER1_CC0_PC3 SILABS_DBUS_TIMER1_CC0(0x2, 0x3)
1426
#define TIMER1_CC0_PC4 SILABS_DBUS_TIMER1_CC0(0x2, 0x4)
1427
#define TIMER1_CC0_PC5 SILABS_DBUS_TIMER1_CC0(0x2, 0x5)
1428
#define TIMER1_CC0_PC6 SILABS_DBUS_TIMER1_CC0(0x2, 0x6)
1429
#define TIMER1_CC0_PC7 SILABS_DBUS_TIMER1_CC0(0x2, 0x7)
1430
#define TIMER1_CC0_PD0 SILABS_DBUS_TIMER1_CC0(0x3, 0x0)
1431
#define TIMER1_CC0_PD1 SILABS_DBUS_TIMER1_CC0(0x3, 0x1)
1432
#define TIMER1_CC0_PD2 SILABS_DBUS_TIMER1_CC0(0x3, 0x2)
1433
#define TIMER1_CC0_PD3 SILABS_DBUS_TIMER1_CC0(0x3, 0x3)
1434
#define TIMER1_CC1_PA0 SILABS_DBUS_TIMER1_CC1(0x0, 0x0)
1435
#define TIMER1_CC1_PA1 SILABS_DBUS_TIMER1_CC1(0x0, 0x1)
1436
#define TIMER1_CC1_PA2 SILABS_DBUS_TIMER1_CC1(0x0, 0x2)
1437
#define TIMER1_CC1_PA3 SILABS_DBUS_TIMER1_CC1(0x0, 0x3)
1438
#define TIMER1_CC1_PA4 SILABS_DBUS_TIMER1_CC1(0x0, 0x4)
1439
#define TIMER1_CC1_PA5 SILABS_DBUS_TIMER1_CC1(0x0, 0x5)
1440
#define TIMER1_CC1_PA6 SILABS_DBUS_TIMER1_CC1(0x0, 0x6)
1441
#define TIMER1_CC1_PA7 SILABS_DBUS_TIMER1_CC1(0x0, 0x7)
1442
#define TIMER1_CC1_PA8 SILABS_DBUS_TIMER1_CC1(0x0, 0x8)
1443
#define TIMER1_CC1_PB0 SILABS_DBUS_TIMER1_CC1(0x1, 0x0)
1444
#define TIMER1_CC1_PB1 SILABS_DBUS_TIMER1_CC1(0x1, 0x1)
1445
#define TIMER1_CC1_PB2 SILABS_DBUS_TIMER1_CC1(0x1, 0x2)
1446
#define TIMER1_CC1_PB3 SILABS_DBUS_TIMER1_CC1(0x1, 0x3)
1447
#define TIMER1_CC1_PB4 SILABS_DBUS_TIMER1_CC1(0x1, 0x4)
1448
#define TIMER1_CC1_PC0 SILABS_DBUS_TIMER1_CC1(0x2, 0x0)
1449
#define TIMER1_CC1_PC1 SILABS_DBUS_TIMER1_CC1(0x2, 0x1)
1450
#define TIMER1_CC1_PC2 SILABS_DBUS_TIMER1_CC1(0x2, 0x2)
1451
#define TIMER1_CC1_PC3 SILABS_DBUS_TIMER1_CC1(0x2, 0x3)
1452
#define TIMER1_CC1_PC4 SILABS_DBUS_TIMER1_CC1(0x2, 0x4)
1453
#define TIMER1_CC1_PC5 SILABS_DBUS_TIMER1_CC1(0x2, 0x5)
1454
#define TIMER1_CC1_PC6 SILABS_DBUS_TIMER1_CC1(0x2, 0x6)
1455
#define TIMER1_CC1_PC7 SILABS_DBUS_TIMER1_CC1(0x2, 0x7)
1456
#define TIMER1_CC1_PD0 SILABS_DBUS_TIMER1_CC1(0x3, 0x0)
1457
#define TIMER1_CC1_PD1 SILABS_DBUS_TIMER1_CC1(0x3, 0x1)
1458
#define TIMER1_CC1_PD2 SILABS_DBUS_TIMER1_CC1(0x3, 0x2)
1459
#define TIMER1_CC1_PD3 SILABS_DBUS_TIMER1_CC1(0x3, 0x3)
1460
#define TIMER1_CC2_PA0 SILABS_DBUS_TIMER1_CC2(0x0, 0x0)
1461
#define TIMER1_CC2_PA1 SILABS_DBUS_TIMER1_CC2(0x0, 0x1)
1462
#define TIMER1_CC2_PA2 SILABS_DBUS_TIMER1_CC2(0x0, 0x2)
1463
#define TIMER1_CC2_PA3 SILABS_DBUS_TIMER1_CC2(0x0, 0x3)
1464
#define TIMER1_CC2_PA4 SILABS_DBUS_TIMER1_CC2(0x0, 0x4)
1465
#define TIMER1_CC2_PA5 SILABS_DBUS_TIMER1_CC2(0x0, 0x5)
1466
#define TIMER1_CC2_PA6 SILABS_DBUS_TIMER1_CC2(0x0, 0x6)
1467
#define TIMER1_CC2_PA7 SILABS_DBUS_TIMER1_CC2(0x0, 0x7)
1468
#define TIMER1_CC2_PA8 SILABS_DBUS_TIMER1_CC2(0x0, 0x8)
1469
#define TIMER1_CC2_PB0 SILABS_DBUS_TIMER1_CC2(0x1, 0x0)
1470
#define TIMER1_CC2_PB1 SILABS_DBUS_TIMER1_CC2(0x1, 0x1)
1471
#define TIMER1_CC2_PB2 SILABS_DBUS_TIMER1_CC2(0x1, 0x2)
1472
#define TIMER1_CC2_PB3 SILABS_DBUS_TIMER1_CC2(0x1, 0x3)
1473
#define TIMER1_CC2_PB4 SILABS_DBUS_TIMER1_CC2(0x1, 0x4)
1474
#define TIMER1_CC2_PC0 SILABS_DBUS_TIMER1_CC2(0x2, 0x0)
1475
#define TIMER1_CC2_PC1 SILABS_DBUS_TIMER1_CC2(0x2, 0x1)
1476
#define TIMER1_CC2_PC2 SILABS_DBUS_TIMER1_CC2(0x2, 0x2)
1477
#define TIMER1_CC2_PC3 SILABS_DBUS_TIMER1_CC2(0x2, 0x3)
1478
#define TIMER1_CC2_PC4 SILABS_DBUS_TIMER1_CC2(0x2, 0x4)
1479
#define TIMER1_CC2_PC5 SILABS_DBUS_TIMER1_CC2(0x2, 0x5)
1480
#define TIMER1_CC2_PC6 SILABS_DBUS_TIMER1_CC2(0x2, 0x6)
1481
#define TIMER1_CC2_PC7 SILABS_DBUS_TIMER1_CC2(0x2, 0x7)
1482
#define TIMER1_CC2_PD0 SILABS_DBUS_TIMER1_CC2(0x3, 0x0)
1483
#define TIMER1_CC2_PD1 SILABS_DBUS_TIMER1_CC2(0x3, 0x1)
1484
#define TIMER1_CC2_PD2 SILABS_DBUS_TIMER1_CC2(0x3, 0x2)
1485
#define TIMER1_CC2_PD3 SILABS_DBUS_TIMER1_CC2(0x3, 0x3)
1486
#define TIMER1_CDTI0_PA0 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x0)
1487
#define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1)
1488
#define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2)
1489
#define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3)
1490
#define TIMER1_CDTI0_PA4 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x4)
1491
#define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5)
1492
#define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6)
1493
#define TIMER1_CDTI0_PA7 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x7)
1494
#define TIMER1_CDTI0_PA8 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x8)
1495
#define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0)
1496
#define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1)
1497
#define TIMER1_CDTI0_PB2 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x2)
1498
#define TIMER1_CDTI0_PB3 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x3)
1499
#define TIMER1_CDTI0_PB4 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x4)
1500
#define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0)
1501
#define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1)
1502
#define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2)
1503
#define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3)
1504
#define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4)
1505
#define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5)
1506
#define TIMER1_CDTI0_PC6 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x6)
1507
#define TIMER1_CDTI0_PC7 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x7)
1508
#define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0)
1509
#define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1)
1510
#define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2)
1511
#define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3)
1512
#define TIMER1_CDTI1_PA0 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x0)
1513
#define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1)
1514
#define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2)
1515
#define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3)
1516
#define TIMER1_CDTI1_PA4 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x4)
1517
#define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5)
1518
#define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6)
1519
#define TIMER1_CDTI1_PA7 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x7)
1520
#define TIMER1_CDTI1_PA8 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x8)
1521
#define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0)
1522
#define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1)
1523
#define TIMER1_CDTI1_PB2 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x2)
1524
#define TIMER1_CDTI1_PB3 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x3)
1525
#define TIMER1_CDTI1_PB4 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x4)
1526
#define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0)
1527
#define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1)
1528
#define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2)
1529
#define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3)
1530
#define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4)
1531
#define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5)
1532
#define TIMER1_CDTI1_PC6 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x6)
1533
#define TIMER1_CDTI1_PC7 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x7)
1534
#define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0)
1535
#define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1)
1536
#define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2)
1537
#define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3)
1538
#define TIMER1_CDTI2_PA0 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x0)
1539
#define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1)
1540
#define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2)
1541
#define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3)
1542
#define TIMER1_CDTI2_PA4 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x4)
1543
#define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5)
1544
#define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6)
1545
#define TIMER1_CDTI2_PA7 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x7)
1546
#define TIMER1_CDTI2_PA8 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x8)
1547
#define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0)
1548
#define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1)
1549
#define TIMER1_CDTI2_PB2 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x2)
1550
#define TIMER1_CDTI2_PB3 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x3)
1551
#define TIMER1_CDTI2_PB4 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x4)
1552
#define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0)
1553
#define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1)
1554
#define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2)
1555
#define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3)
1556
#define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4)
1557
#define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5)
1558
#define TIMER1_CDTI2_PC6 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x6)
1559
#define TIMER1_CDTI2_PC7 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x7)
1560
#define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0)
1561
#define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1)
1562
#define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2)
1563
#define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3)
1564
1565
#define TIMER2_CC0_PA0 SILABS_DBUS_TIMER2_CC0(0x0, 0x0)
1566
#define TIMER2_CC0_PA1 SILABS_DBUS_TIMER2_CC0(0x0, 0x1)
1567
#define TIMER2_CC0_PA2 SILABS_DBUS_TIMER2_CC0(0x0, 0x2)
1568
#define TIMER2_CC0_PA3 SILABS_DBUS_TIMER2_CC0(0x0, 0x3)
1569
#define TIMER2_CC0_PA4 SILABS_DBUS_TIMER2_CC0(0x0, 0x4)
1570
#define TIMER2_CC0_PA5 SILABS_DBUS_TIMER2_CC0(0x0, 0x5)
1571
#define TIMER2_CC0_PA6 SILABS_DBUS_TIMER2_CC0(0x0, 0x6)
1572
#define TIMER2_CC0_PA7 SILABS_DBUS_TIMER2_CC0(0x0, 0x7)
1573
#define TIMER2_CC0_PA8 SILABS_DBUS_TIMER2_CC0(0x0, 0x8)
1574
#define TIMER2_CC0_PB0 SILABS_DBUS_TIMER2_CC0(0x1, 0x0)
1575
#define TIMER2_CC0_PB1 SILABS_DBUS_TIMER2_CC0(0x1, 0x1)
1576
#define TIMER2_CC0_PB2 SILABS_DBUS_TIMER2_CC0(0x1, 0x2)
1577
#define TIMER2_CC0_PB3 SILABS_DBUS_TIMER2_CC0(0x1, 0x3)
1578
#define TIMER2_CC0_PB4 SILABS_DBUS_TIMER2_CC0(0x1, 0x4)
1579
#define TIMER2_CC1_PA0 SILABS_DBUS_TIMER2_CC1(0x0, 0x0)
1580
#define TIMER2_CC1_PA1 SILABS_DBUS_TIMER2_CC1(0x0, 0x1)
1581
#define TIMER2_CC1_PA2 SILABS_DBUS_TIMER2_CC1(0x0, 0x2)
1582
#define TIMER2_CC1_PA3 SILABS_DBUS_TIMER2_CC1(0x0, 0x3)
1583
#define TIMER2_CC1_PA4 SILABS_DBUS_TIMER2_CC1(0x0, 0x4)
1584
#define TIMER2_CC1_PA5 SILABS_DBUS_TIMER2_CC1(0x0, 0x5)
1585
#define TIMER2_CC1_PA6 SILABS_DBUS_TIMER2_CC1(0x0, 0x6)
1586
#define TIMER2_CC1_PA7 SILABS_DBUS_TIMER2_CC1(0x0, 0x7)
1587
#define TIMER2_CC1_PA8 SILABS_DBUS_TIMER2_CC1(0x0, 0x8)
1588
#define TIMER2_CC1_PB0 SILABS_DBUS_TIMER2_CC1(0x1, 0x0)
1589
#define TIMER2_CC1_PB1 SILABS_DBUS_TIMER2_CC1(0x1, 0x1)
1590
#define TIMER2_CC1_PB2 SILABS_DBUS_TIMER2_CC1(0x1, 0x2)
1591
#define TIMER2_CC1_PB3 SILABS_DBUS_TIMER2_CC1(0x1, 0x3)
1592
#define TIMER2_CC1_PB4 SILABS_DBUS_TIMER2_CC1(0x1, 0x4)
1593
#define TIMER2_CC2_PA0 SILABS_DBUS_TIMER2_CC2(0x0, 0x0)
1594
#define TIMER2_CC2_PA1 SILABS_DBUS_TIMER2_CC2(0x0, 0x1)
1595
#define TIMER2_CC2_PA2 SILABS_DBUS_TIMER2_CC2(0x0, 0x2)
1596
#define TIMER2_CC2_PA3 SILABS_DBUS_TIMER2_CC2(0x0, 0x3)
1597
#define TIMER2_CC2_PA4 SILABS_DBUS_TIMER2_CC2(0x0, 0x4)
1598
#define TIMER2_CC2_PA5 SILABS_DBUS_TIMER2_CC2(0x0, 0x5)
1599
#define TIMER2_CC2_PA6 SILABS_DBUS_TIMER2_CC2(0x0, 0x6)
1600
#define TIMER2_CC2_PA7 SILABS_DBUS_TIMER2_CC2(0x0, 0x7)
1601
#define TIMER2_CC2_PA8 SILABS_DBUS_TIMER2_CC2(0x0, 0x8)
1602
#define TIMER2_CC2_PB0 SILABS_DBUS_TIMER2_CC2(0x1, 0x0)
1603
#define TIMER2_CC2_PB1 SILABS_DBUS_TIMER2_CC2(0x1, 0x1)
1604
#define TIMER2_CC2_PB2 SILABS_DBUS_TIMER2_CC2(0x1, 0x2)
1605
#define TIMER2_CC2_PB3 SILABS_DBUS_TIMER2_CC2(0x1, 0x3)
1606
#define TIMER2_CC2_PB4 SILABS_DBUS_TIMER2_CC2(0x1, 0x4)
1607
#define TIMER2_CDTI0_PA0 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x0)
1608
#define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1)
1609
#define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2)
1610
#define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3)
1611
#define TIMER2_CDTI0_PA4 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x4)
1612
#define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5)
1613
#define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6)
1614
#define TIMER2_CDTI0_PA7 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x7)
1615
#define TIMER2_CDTI0_PA8 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x8)
1616
#define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0)
1617
#define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1)
1618
#define TIMER2_CDTI0_PB2 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x2)
1619
#define TIMER2_CDTI0_PB3 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x3)
1620
#define TIMER2_CDTI0_PB4 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x4)
1621
#define TIMER2_CDTI1_PA0 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x0)
1622
#define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1)
1623
#define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2)
1624
#define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3)
1625
#define TIMER2_CDTI1_PA4 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x4)
1626
#define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5)
1627
#define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6)
1628
#define TIMER2_CDTI1_PA7 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x7)
1629
#define TIMER2_CDTI1_PA8 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x8)
1630
#define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0)
1631
#define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1)
1632
#define TIMER2_CDTI1_PB2 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x2)
1633
#define TIMER2_CDTI1_PB3 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x3)
1634
#define TIMER2_CDTI1_PB4 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x4)
1635
#define TIMER2_CDTI2_PA0 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x0)
1636
#define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1)
1637
#define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2)
1638
#define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3)
1639
#define TIMER2_CDTI2_PA4 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x4)
1640
#define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5)
1641
#define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6)
1642
#define TIMER2_CDTI2_PA7 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x7)
1643
#define TIMER2_CDTI2_PA8 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x8)
1644
#define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0)
1645
#define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1)
1646
#define TIMER2_CDTI2_PB2 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x2)
1647
#define TIMER2_CDTI2_PB3 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x3)
1648
#define TIMER2_CDTI2_PB4 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x4)
1649
1650
#define TIMER3_CC0_PC0 SILABS_DBUS_TIMER3_CC0(0x2, 0x0)
1651
#define TIMER3_CC0_PC1 SILABS_DBUS_TIMER3_CC0(0x2, 0x1)
1652
#define TIMER3_CC0_PC2 SILABS_DBUS_TIMER3_CC0(0x2, 0x2)
1653
#define TIMER3_CC0_PC3 SILABS_DBUS_TIMER3_CC0(0x2, 0x3)
1654
#define TIMER3_CC0_PC4 SILABS_DBUS_TIMER3_CC0(0x2, 0x4)
1655
#define TIMER3_CC0_PC5 SILABS_DBUS_TIMER3_CC0(0x2, 0x5)
1656
#define TIMER3_CC0_PC6 SILABS_DBUS_TIMER3_CC0(0x2, 0x6)
1657
#define TIMER3_CC0_PC7 SILABS_DBUS_TIMER3_CC0(0x2, 0x7)
1658
#define TIMER3_CC0_PD0 SILABS_DBUS_TIMER3_CC0(0x3, 0x0)
1659
#define TIMER3_CC0_PD1 SILABS_DBUS_TIMER3_CC0(0x3, 0x1)
1660
#define TIMER3_CC0_PD2 SILABS_DBUS_TIMER3_CC0(0x3, 0x2)
1661
#define TIMER3_CC0_PD3 SILABS_DBUS_TIMER3_CC0(0x3, 0x3)
1662
#define TIMER3_CC1_PC0 SILABS_DBUS_TIMER3_CC1(0x2, 0x0)
1663
#define TIMER3_CC1_PC1 SILABS_DBUS_TIMER3_CC1(0x2, 0x1)
1664
#define TIMER3_CC1_PC2 SILABS_DBUS_TIMER3_CC1(0x2, 0x2)
1665
#define TIMER3_CC1_PC3 SILABS_DBUS_TIMER3_CC1(0x2, 0x3)
1666
#define TIMER3_CC1_PC4 SILABS_DBUS_TIMER3_CC1(0x2, 0x4)
1667
#define TIMER3_CC1_PC5 SILABS_DBUS_TIMER3_CC1(0x2, 0x5)
1668
#define TIMER3_CC1_PC6 SILABS_DBUS_TIMER3_CC1(0x2, 0x6)
1669
#define TIMER3_CC1_PC7 SILABS_DBUS_TIMER3_CC1(0x2, 0x7)
1670
#define TIMER3_CC1_PD0 SILABS_DBUS_TIMER3_CC1(0x3, 0x0)
1671
#define TIMER3_CC1_PD1 SILABS_DBUS_TIMER3_CC1(0x3, 0x1)
1672
#define TIMER3_CC1_PD2 SILABS_DBUS_TIMER3_CC1(0x3, 0x2)
1673
#define TIMER3_CC1_PD3 SILABS_DBUS_TIMER3_CC1(0x3, 0x3)
1674
#define TIMER3_CC2_PC0 SILABS_DBUS_TIMER3_CC2(0x2, 0x0)
1675
#define TIMER3_CC2_PC1 SILABS_DBUS_TIMER3_CC2(0x2, 0x1)
1676
#define TIMER3_CC2_PC2 SILABS_DBUS_TIMER3_CC2(0x2, 0x2)
1677
#define TIMER3_CC2_PC3 SILABS_DBUS_TIMER3_CC2(0x2, 0x3)
1678
#define TIMER3_CC2_PC4 SILABS_DBUS_TIMER3_CC2(0x2, 0x4)
1679
#define TIMER3_CC2_PC5 SILABS_DBUS_TIMER3_CC2(0x2, 0x5)
1680
#define TIMER3_CC2_PC6 SILABS_DBUS_TIMER3_CC2(0x2, 0x6)
1681
#define TIMER3_CC2_PC7 SILABS_DBUS_TIMER3_CC2(0x2, 0x7)
1682
#define TIMER3_CC2_PD0 SILABS_DBUS_TIMER3_CC2(0x3, 0x0)
1683
#define TIMER3_CC2_PD1 SILABS_DBUS_TIMER3_CC2(0x3, 0x1)
1684
#define TIMER3_CC2_PD2 SILABS_DBUS_TIMER3_CC2(0x3, 0x2)
1685
#define TIMER3_CC2_PD3 SILABS_DBUS_TIMER3_CC2(0x3, 0x3)
1686
#define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0)
1687
#define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1)
1688
#define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2)
1689
#define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3)
1690
#define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4)
1691
#define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5)
1692
#define TIMER3_CDTI0_PC6 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x6)
1693
#define TIMER3_CDTI0_PC7 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x7)
1694
#define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0)
1695
#define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1)
1696
#define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2)
1697
#define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3)
1698
#define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0)
1699
#define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1)
1700
#define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2)
1701
#define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3)
1702
#define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4)
1703
#define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5)
1704
#define TIMER3_CDTI1_PC6 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x6)
1705
#define TIMER3_CDTI1_PC7 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x7)
1706
#define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0)
1707
#define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1)
1708
#define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2)
1709
#define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3)
1710
#define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0)
1711
#define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1)
1712
#define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2)
1713
#define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3)
1714
#define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4)
1715
#define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5)
1716
#define TIMER3_CDTI2_PC6 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x6)
1717
#define TIMER3_CDTI2_PC7 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x7)
1718
#define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0)
1719
#define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1)
1720
#define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2)
1721
#define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3)
1722
1723
#define TIMER4_CC0_PA0 SILABS_DBUS_TIMER4_CC0(0x0, 0x0)
1724
#define TIMER4_CC0_PA1 SILABS_DBUS_TIMER4_CC0(0x0, 0x1)
1725
#define TIMER4_CC0_PA2 SILABS_DBUS_TIMER4_CC0(0x0, 0x2)
1726
#define TIMER4_CC0_PA3 SILABS_DBUS_TIMER4_CC0(0x0, 0x3)
1727
#define TIMER4_CC0_PA4 SILABS_DBUS_TIMER4_CC0(0x0, 0x4)
1728
#define TIMER4_CC0_PA5 SILABS_DBUS_TIMER4_CC0(0x0, 0x5)
1729
#define TIMER4_CC0_PA6 SILABS_DBUS_TIMER4_CC0(0x0, 0x6)
1730
#define TIMER4_CC0_PA7 SILABS_DBUS_TIMER4_CC0(0x0, 0x7)
1731
#define TIMER4_CC0_PA8 SILABS_DBUS_TIMER4_CC0(0x0, 0x8)
1732
#define TIMER4_CC0_PB0 SILABS_DBUS_TIMER4_CC0(0x1, 0x0)
1733
#define TIMER4_CC0_PB1 SILABS_DBUS_TIMER4_CC0(0x1, 0x1)
1734
#define TIMER4_CC0_PB2 SILABS_DBUS_TIMER4_CC0(0x1, 0x2)
1735
#define TIMER4_CC0_PB3 SILABS_DBUS_TIMER4_CC0(0x1, 0x3)
1736
#define TIMER4_CC0_PB4 SILABS_DBUS_TIMER4_CC0(0x1, 0x4)
1737
#define TIMER4_CC1_PA0 SILABS_DBUS_TIMER4_CC1(0x0, 0x0)
1738
#define TIMER4_CC1_PA1 SILABS_DBUS_TIMER4_CC1(0x0, 0x1)
1739
#define TIMER4_CC1_PA2 SILABS_DBUS_TIMER4_CC1(0x0, 0x2)
1740
#define TIMER4_CC1_PA3 SILABS_DBUS_TIMER4_CC1(0x0, 0x3)
1741
#define TIMER4_CC1_PA4 SILABS_DBUS_TIMER4_CC1(0x0, 0x4)
1742
#define TIMER4_CC1_PA5 SILABS_DBUS_TIMER4_CC1(0x0, 0x5)
1743
#define TIMER4_CC1_PA6 SILABS_DBUS_TIMER4_CC1(0x0, 0x6)
1744
#define TIMER4_CC1_PA7 SILABS_DBUS_TIMER4_CC1(0x0, 0x7)
1745
#define TIMER4_CC1_PA8 SILABS_DBUS_TIMER4_CC1(0x0, 0x8)
1746
#define TIMER4_CC1_PB0 SILABS_DBUS_TIMER4_CC1(0x1, 0x0)
1747
#define TIMER4_CC1_PB1 SILABS_DBUS_TIMER4_CC1(0x1, 0x1)
1748
#define TIMER4_CC1_PB2 SILABS_DBUS_TIMER4_CC1(0x1, 0x2)
1749
#define TIMER4_CC1_PB3 SILABS_DBUS_TIMER4_CC1(0x1, 0x3)
1750
#define TIMER4_CC1_PB4 SILABS_DBUS_TIMER4_CC1(0x1, 0x4)
1751
#define TIMER4_CC2_PA0 SILABS_DBUS_TIMER4_CC2(0x0, 0x0)
1752
#define TIMER4_CC2_PA1 SILABS_DBUS_TIMER4_CC2(0x0, 0x1)
1753
#define TIMER4_CC2_PA2 SILABS_DBUS_TIMER4_CC2(0x0, 0x2)
1754
#define TIMER4_CC2_PA3 SILABS_DBUS_TIMER4_CC2(0x0, 0x3)
1755
#define TIMER4_CC2_PA4 SILABS_DBUS_TIMER4_CC2(0x0, 0x4)
1756
#define TIMER4_CC2_PA5 SILABS_DBUS_TIMER4_CC2(0x0, 0x5)
1757
#define TIMER4_CC2_PA6 SILABS_DBUS_TIMER4_CC2(0x0, 0x6)
1758
#define TIMER4_CC2_PA7 SILABS_DBUS_TIMER4_CC2(0x0, 0x7)
1759
#define TIMER4_CC2_PA8 SILABS_DBUS_TIMER4_CC2(0x0, 0x8)
1760
#define TIMER4_CC2_PB0 SILABS_DBUS_TIMER4_CC2(0x1, 0x0)
1761
#define TIMER4_CC2_PB1 SILABS_DBUS_TIMER4_CC2(0x1, 0x1)
1762
#define TIMER4_CC2_PB2 SILABS_DBUS_TIMER4_CC2(0x1, 0x2)
1763
#define TIMER4_CC2_PB3 SILABS_DBUS_TIMER4_CC2(0x1, 0x3)
1764
#define TIMER4_CC2_PB4 SILABS_DBUS_TIMER4_CC2(0x1, 0x4)
1765
#define TIMER4_CDTI0_PA0 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x0)
1766
#define TIMER4_CDTI0_PA1 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x1)
1767
#define TIMER4_CDTI0_PA2 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x2)
1768
#define TIMER4_CDTI0_PA3 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x3)
1769
#define TIMER4_CDTI0_PA4 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x4)
1770
#define TIMER4_CDTI0_PA5 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x5)
1771
#define TIMER4_CDTI0_PA6 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x6)
1772
#define TIMER4_CDTI0_PA7 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x7)
1773
#define TIMER4_CDTI0_PA8 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x8)
1774
#define TIMER4_CDTI0_PB0 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x0)
1775
#define TIMER4_CDTI0_PB1 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x1)
1776
#define TIMER4_CDTI0_PB2 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x2)
1777
#define TIMER4_CDTI0_PB3 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x3)
1778
#define TIMER4_CDTI0_PB4 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x4)
1779
#define TIMER4_CDTI1_PA0 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x0)
1780
#define TIMER4_CDTI1_PA1 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x1)
1781
#define TIMER4_CDTI1_PA2 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x2)
1782
#define TIMER4_CDTI1_PA3 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x3)
1783
#define TIMER4_CDTI1_PA4 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x4)
1784
#define TIMER4_CDTI1_PA5 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x5)
1785
#define TIMER4_CDTI1_PA6 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x6)
1786
#define TIMER4_CDTI1_PA7 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x7)
1787
#define TIMER4_CDTI1_PA8 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x8)
1788
#define TIMER4_CDTI1_PB0 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x0)
1789
#define TIMER4_CDTI1_PB1 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x1)
1790
#define TIMER4_CDTI1_PB2 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x2)
1791
#define TIMER4_CDTI1_PB3 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x3)
1792
#define TIMER4_CDTI1_PB4 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x4)
1793
#define TIMER4_CDTI2_PA0 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x0)
1794
#define TIMER4_CDTI2_PA1 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x1)
1795
#define TIMER4_CDTI2_PA2 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x2)
1796
#define TIMER4_CDTI2_PA3 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x3)
1797
#define TIMER4_CDTI2_PA4 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x4)
1798
#define TIMER4_CDTI2_PA5 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x5)
1799
#define TIMER4_CDTI2_PA6 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x6)
1800
#define TIMER4_CDTI2_PA7 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x7)
1801
#define TIMER4_CDTI2_PA8 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x8)
1802
#define TIMER4_CDTI2_PB0 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x0)
1803
#define TIMER4_CDTI2_PB1 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x1)
1804
#define TIMER4_CDTI2_PB2 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x2)
1805
#define TIMER4_CDTI2_PB3 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x3)
1806
#define TIMER4_CDTI2_PB4 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x4)
1807
1808
#define USART0_CS_PA0 SILABS_DBUS_USART0_CS(0x0, 0x0)
1809
#define USART0_CS_PA1 SILABS_DBUS_USART0_CS(0x0, 0x1)
1810
#define USART0_CS_PA2 SILABS_DBUS_USART0_CS(0x0, 0x2)
1811
#define USART0_CS_PA3 SILABS_DBUS_USART0_CS(0x0, 0x3)
1812
#define USART0_CS_PA4 SILABS_DBUS_USART0_CS(0x0, 0x4)
1813
#define USART0_CS_PA5 SILABS_DBUS_USART0_CS(0x0, 0x5)
1814
#define USART0_CS_PA6 SILABS_DBUS_USART0_CS(0x0, 0x6)
1815
#define USART0_CS_PA7 SILABS_DBUS_USART0_CS(0x0, 0x7)
1816
#define USART0_CS_PA8 SILABS_DBUS_USART0_CS(0x0, 0x8)
1817
#define USART0_CS_PB0 SILABS_DBUS_USART0_CS(0x1, 0x0)
1818
#define USART0_CS_PB1 SILABS_DBUS_USART0_CS(0x1, 0x1)
1819
#define USART0_CS_PB2 SILABS_DBUS_USART0_CS(0x1, 0x2)
1820
#define USART0_CS_PB3 SILABS_DBUS_USART0_CS(0x1, 0x3)
1821
#define USART0_CS_PB4 SILABS_DBUS_USART0_CS(0x1, 0x4)
1822
#define USART0_CS_PC0 SILABS_DBUS_USART0_CS(0x2, 0x0)
1823
#define USART0_CS_PC1 SILABS_DBUS_USART0_CS(0x2, 0x1)
1824
#define USART0_CS_PC2 SILABS_DBUS_USART0_CS(0x2, 0x2)
1825
#define USART0_CS_PC3 SILABS_DBUS_USART0_CS(0x2, 0x3)
1826
#define USART0_CS_PC4 SILABS_DBUS_USART0_CS(0x2, 0x4)
1827
#define USART0_CS_PC5 SILABS_DBUS_USART0_CS(0x2, 0x5)
1828
#define USART0_CS_PC6 SILABS_DBUS_USART0_CS(0x2, 0x6)
1829
#define USART0_CS_PC7 SILABS_DBUS_USART0_CS(0x2, 0x7)
1830
#define USART0_CS_PD0 SILABS_DBUS_USART0_CS(0x3, 0x0)
1831
#define USART0_CS_PD1 SILABS_DBUS_USART0_CS(0x3, 0x1)
1832
#define USART0_CS_PD2 SILABS_DBUS_USART0_CS(0x3, 0x2)
1833
#define USART0_CS_PD3 SILABS_DBUS_USART0_CS(0x3, 0x3)
1834
#define USART0_RTS_PA0 SILABS_DBUS_USART0_RTS(0x0, 0x0)
1835
#define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1)
1836
#define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2)
1837
#define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3)
1838
#define USART0_RTS_PA4 SILABS_DBUS_USART0_RTS(0x0, 0x4)
1839
#define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5)
1840
#define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6)
1841
#define USART0_RTS_PA7 SILABS_DBUS_USART0_RTS(0x0, 0x7)
1842
#define USART0_RTS_PA8 SILABS_DBUS_USART0_RTS(0x0, 0x8)
1843
#define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0)
1844
#define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1)
1845
#define USART0_RTS_PB2 SILABS_DBUS_USART0_RTS(0x1, 0x2)
1846
#define USART0_RTS_PB3 SILABS_DBUS_USART0_RTS(0x1, 0x3)
1847
#define USART0_RTS_PB4 SILABS_DBUS_USART0_RTS(0x1, 0x4)
1848
#define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0)
1849
#define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1)
1850
#define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2)
1851
#define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3)
1852
#define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4)
1853
#define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5)
1854
#define USART0_RTS_PC6 SILABS_DBUS_USART0_RTS(0x2, 0x6)
1855
#define USART0_RTS_PC7 SILABS_DBUS_USART0_RTS(0x2, 0x7)
1856
#define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0)
1857
#define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1)
1858
#define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2)
1859
#define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3)
1860
#define USART0_RX_PA0 SILABS_DBUS_USART0_RX(0x0, 0x0)
1861
#define USART0_RX_PA1 SILABS_DBUS_USART0_RX(0x0, 0x1)
1862
#define USART0_RX_PA2 SILABS_DBUS_USART0_RX(0x0, 0x2)
1863
#define USART0_RX_PA3 SILABS_DBUS_USART0_RX(0x0, 0x3)
1864
#define USART0_RX_PA4 SILABS_DBUS_USART0_RX(0x0, 0x4)
1865
#define USART0_RX_PA5 SILABS_DBUS_USART0_RX(0x0, 0x5)
1866
#define USART0_RX_PA6 SILABS_DBUS_USART0_RX(0x0, 0x6)
1867
#define USART0_RX_PA7 SILABS_DBUS_USART0_RX(0x0, 0x7)
1868
#define USART0_RX_PA8 SILABS_DBUS_USART0_RX(0x0, 0x8)
1869
#define USART0_RX_PB0 SILABS_DBUS_USART0_RX(0x1, 0x0)
1870
#define USART0_RX_PB1 SILABS_DBUS_USART0_RX(0x1, 0x1)
1871
#define USART0_RX_PB2 SILABS_DBUS_USART0_RX(0x1, 0x2)
1872
#define USART0_RX_PB3 SILABS_DBUS_USART0_RX(0x1, 0x3)
1873
#define USART0_RX_PB4 SILABS_DBUS_USART0_RX(0x1, 0x4)
1874
#define USART0_RX_PC0 SILABS_DBUS_USART0_RX(0x2, 0x0)
1875
#define USART0_RX_PC1 SILABS_DBUS_USART0_RX(0x2, 0x1)
1876
#define USART0_RX_PC2 SILABS_DBUS_USART0_RX(0x2, 0x2)
1877
#define USART0_RX_PC3 SILABS_DBUS_USART0_RX(0x2, 0x3)
1878
#define USART0_RX_PC4 SILABS_DBUS_USART0_RX(0x2, 0x4)
1879
#define USART0_RX_PC5 SILABS_DBUS_USART0_RX(0x2, 0x5)
1880
#define USART0_RX_PC6 SILABS_DBUS_USART0_RX(0x2, 0x6)
1881
#define USART0_RX_PC7 SILABS_DBUS_USART0_RX(0x2, 0x7)
1882
#define USART0_RX_PD0 SILABS_DBUS_USART0_RX(0x3, 0x0)
1883
#define USART0_RX_PD1 SILABS_DBUS_USART0_RX(0x3, 0x1)
1884
#define USART0_RX_PD2 SILABS_DBUS_USART0_RX(0x3, 0x2)
1885
#define USART0_RX_PD3 SILABS_DBUS_USART0_RX(0x3, 0x3)
1886
#define USART0_CLK_PA0 SILABS_DBUS_USART0_CLK(0x0, 0x0)
1887
#define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1)
1888
#define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2)
1889
#define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3)
1890
#define USART0_CLK_PA4 SILABS_DBUS_USART0_CLK(0x0, 0x4)
1891
#define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5)
1892
#define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6)
1893
#define USART0_CLK_PA7 SILABS_DBUS_USART0_CLK(0x0, 0x7)
1894
#define USART0_CLK_PA8 SILABS_DBUS_USART0_CLK(0x0, 0x8)
1895
#define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0)
1896
#define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1)
1897
#define USART0_CLK_PB2 SILABS_DBUS_USART0_CLK(0x1, 0x2)
1898
#define USART0_CLK_PB3 SILABS_DBUS_USART0_CLK(0x1, 0x3)
1899
#define USART0_CLK_PB4 SILABS_DBUS_USART0_CLK(0x1, 0x4)
1900
#define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0)
1901
#define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1)
1902
#define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2)
1903
#define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3)
1904
#define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4)
1905
#define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5)
1906
#define USART0_CLK_PC6 SILABS_DBUS_USART0_CLK(0x2, 0x6)
1907
#define USART0_CLK_PC7 SILABS_DBUS_USART0_CLK(0x2, 0x7)
1908
#define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0)
1909
#define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1)
1910
#define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2)
1911
#define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3)
1912
#define USART0_TX_PA0 SILABS_DBUS_USART0_TX(0x0, 0x0)
1913
#define USART0_TX_PA1 SILABS_DBUS_USART0_TX(0x0, 0x1)
1914
#define USART0_TX_PA2 SILABS_DBUS_USART0_TX(0x0, 0x2)
1915
#define USART0_TX_PA3 SILABS_DBUS_USART0_TX(0x0, 0x3)
1916
#define USART0_TX_PA4 SILABS_DBUS_USART0_TX(0x0, 0x4)
1917
#define USART0_TX_PA5 SILABS_DBUS_USART0_TX(0x0, 0x5)
1918
#define USART0_TX_PA6 SILABS_DBUS_USART0_TX(0x0, 0x6)
1919
#define USART0_TX_PA7 SILABS_DBUS_USART0_TX(0x0, 0x7)
1920
#define USART0_TX_PA8 SILABS_DBUS_USART0_TX(0x0, 0x8)
1921
#define USART0_TX_PB0 SILABS_DBUS_USART0_TX(0x1, 0x0)
1922
#define USART0_TX_PB1 SILABS_DBUS_USART0_TX(0x1, 0x1)
1923
#define USART0_TX_PB2 SILABS_DBUS_USART0_TX(0x1, 0x2)
1924
#define USART0_TX_PB3 SILABS_DBUS_USART0_TX(0x1, 0x3)
1925
#define USART0_TX_PB4 SILABS_DBUS_USART0_TX(0x1, 0x4)
1926
#define USART0_TX_PC0 SILABS_DBUS_USART0_TX(0x2, 0x0)
1927
#define USART0_TX_PC1 SILABS_DBUS_USART0_TX(0x2, 0x1)
1928
#define USART0_TX_PC2 SILABS_DBUS_USART0_TX(0x2, 0x2)
1929
#define USART0_TX_PC3 SILABS_DBUS_USART0_TX(0x2, 0x3)
1930
#define USART0_TX_PC4 SILABS_DBUS_USART0_TX(0x2, 0x4)
1931
#define USART0_TX_PC5 SILABS_DBUS_USART0_TX(0x2, 0x5)
1932
#define USART0_TX_PC6 SILABS_DBUS_USART0_TX(0x2, 0x6)
1933
#define USART0_TX_PC7 SILABS_DBUS_USART0_TX(0x2, 0x7)
1934
#define USART0_TX_PD0 SILABS_DBUS_USART0_TX(0x3, 0x0)
1935
#define USART0_TX_PD1 SILABS_DBUS_USART0_TX(0x3, 0x1)
1936
#define USART0_TX_PD2 SILABS_DBUS_USART0_TX(0x3, 0x2)
1937
#define USART0_TX_PD3 SILABS_DBUS_USART0_TX(0x3, 0x3)
1938
#define USART0_CTS_PA0 SILABS_DBUS_USART0_CTS(0x0, 0x0)
1939
#define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1)
1940
#define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2)
1941
#define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3)
1942
#define USART0_CTS_PA4 SILABS_DBUS_USART0_CTS(0x0, 0x4)
1943
#define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5)
1944
#define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6)
1945
#define USART0_CTS_PA7 SILABS_DBUS_USART0_CTS(0x0, 0x7)
1946
#define USART0_CTS_PA8 SILABS_DBUS_USART0_CTS(0x0, 0x8)
1947
#define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0)
1948
#define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1)
1949
#define USART0_CTS_PB2 SILABS_DBUS_USART0_CTS(0x1, 0x2)
1950
#define USART0_CTS_PB3 SILABS_DBUS_USART0_CTS(0x1, 0x3)
1951
#define USART0_CTS_PB4 SILABS_DBUS_USART0_CTS(0x1, 0x4)
1952
#define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0)
1953
#define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1)
1954
#define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2)
1955
#define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3)
1956
#define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4)
1957
#define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5)
1958
#define USART0_CTS_PC6 SILABS_DBUS_USART0_CTS(0x2, 0x6)
1959
#define USART0_CTS_PC7 SILABS_DBUS_USART0_CTS(0x2, 0x7)
1960
#define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0)
1961
#define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1)
1962
#define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2)
1963
#define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3)
1964
1965
#define USART1_CS_PA0 SILABS_DBUS_USART1_CS(0x0, 0x0)
1966
#define USART1_CS_PA1 SILABS_DBUS_USART1_CS(0x0, 0x1)
1967
#define USART1_CS_PA2 SILABS_DBUS_USART1_CS(0x0, 0x2)
1968
#define USART1_CS_PA3 SILABS_DBUS_USART1_CS(0x0, 0x3)
1969
#define USART1_CS_PA4 SILABS_DBUS_USART1_CS(0x0, 0x4)
1970
#define USART1_CS_PA5 SILABS_DBUS_USART1_CS(0x0, 0x5)
1971
#define USART1_CS_PA6 SILABS_DBUS_USART1_CS(0x0, 0x6)
1972
#define USART1_CS_PA7 SILABS_DBUS_USART1_CS(0x0, 0x7)
1973
#define USART1_CS_PA8 SILABS_DBUS_USART1_CS(0x0, 0x8)
1974
#define USART1_CS_PB0 SILABS_DBUS_USART1_CS(0x1, 0x0)
1975
#define USART1_CS_PB1 SILABS_DBUS_USART1_CS(0x1, 0x1)
1976
#define USART1_CS_PB2 SILABS_DBUS_USART1_CS(0x1, 0x2)
1977
#define USART1_CS_PB3 SILABS_DBUS_USART1_CS(0x1, 0x3)
1978
#define USART1_CS_PB4 SILABS_DBUS_USART1_CS(0x1, 0x4)
1979
#define USART1_RTS_PA0 SILABS_DBUS_USART1_RTS(0x0, 0x0)
1980
#define USART1_RTS_PA1 SILABS_DBUS_USART1_RTS(0x0, 0x1)
1981
#define USART1_RTS_PA2 SILABS_DBUS_USART1_RTS(0x0, 0x2)
1982
#define USART1_RTS_PA3 SILABS_DBUS_USART1_RTS(0x0, 0x3)
1983
#define USART1_RTS_PA4 SILABS_DBUS_USART1_RTS(0x0, 0x4)
1984
#define USART1_RTS_PA5 SILABS_DBUS_USART1_RTS(0x0, 0x5)
1985
#define USART1_RTS_PA6 SILABS_DBUS_USART1_RTS(0x0, 0x6)
1986
#define USART1_RTS_PA7 SILABS_DBUS_USART1_RTS(0x0, 0x7)
1987
#define USART1_RTS_PA8 SILABS_DBUS_USART1_RTS(0x0, 0x8)
1988
#define USART1_RTS_PB0 SILABS_DBUS_USART1_RTS(0x1, 0x0)
1989
#define USART1_RTS_PB1 SILABS_DBUS_USART1_RTS(0x1, 0x1)
1990
#define USART1_RTS_PB2 SILABS_DBUS_USART1_RTS(0x1, 0x2)
1991
#define USART1_RTS_PB3 SILABS_DBUS_USART1_RTS(0x1, 0x3)
1992
#define USART1_RTS_PB4 SILABS_DBUS_USART1_RTS(0x1, 0x4)
1993
#define USART1_RX_PA0 SILABS_DBUS_USART1_RX(0x0, 0x0)
1994
#define USART1_RX_PA1 SILABS_DBUS_USART1_RX(0x0, 0x1)
1995
#define USART1_RX_PA2 SILABS_DBUS_USART1_RX(0x0, 0x2)
1996
#define USART1_RX_PA3 SILABS_DBUS_USART1_RX(0x0, 0x3)
1997
#define USART1_RX_PA4 SILABS_DBUS_USART1_RX(0x0, 0x4)
1998
#define USART1_RX_PA5 SILABS_DBUS_USART1_RX(0x0, 0x5)
1999
#define USART1_RX_PA6 SILABS_DBUS_USART1_RX(0x0, 0x6)
2000
#define USART1_RX_PA7 SILABS_DBUS_USART1_RX(0x0, 0x7)
2001
#define USART1_RX_PA8 SILABS_DBUS_USART1_RX(0x0, 0x8)
2002
#define USART1_RX_PB0 SILABS_DBUS_USART1_RX(0x1, 0x0)
2003
#define USART1_RX_PB1 SILABS_DBUS_USART1_RX(0x1, 0x1)
2004
#define USART1_RX_PB2 SILABS_DBUS_USART1_RX(0x1, 0x2)
2005
#define USART1_RX_PB3 SILABS_DBUS_USART1_RX(0x1, 0x3)
2006
#define USART1_RX_PB4 SILABS_DBUS_USART1_RX(0x1, 0x4)
2007
#define USART1_CLK_PA0 SILABS_DBUS_USART1_CLK(0x0, 0x0)
2008
#define USART1_CLK_PA1 SILABS_DBUS_USART1_CLK(0x0, 0x1)
2009
#define USART1_CLK_PA2 SILABS_DBUS_USART1_CLK(0x0, 0x2)
2010
#define USART1_CLK_PA3 SILABS_DBUS_USART1_CLK(0x0, 0x3)
2011
#define USART1_CLK_PA4 SILABS_DBUS_USART1_CLK(0x0, 0x4)
2012
#define USART1_CLK_PA5 SILABS_DBUS_USART1_CLK(0x0, 0x5)
2013
#define USART1_CLK_PA6 SILABS_DBUS_USART1_CLK(0x0, 0x6)
2014
#define USART1_CLK_PA7 SILABS_DBUS_USART1_CLK(0x0, 0x7)
2015
#define USART1_CLK_PA8 SILABS_DBUS_USART1_CLK(0x0, 0x8)
2016
#define USART1_CLK_PB0 SILABS_DBUS_USART1_CLK(0x1, 0x0)
2017
#define USART1_CLK_PB1 SILABS_DBUS_USART1_CLK(0x1, 0x1)
2018
#define USART1_CLK_PB2 SILABS_DBUS_USART1_CLK(0x1, 0x2)
2019
#define USART1_CLK_PB3 SILABS_DBUS_USART1_CLK(0x1, 0x3)
2020
#define USART1_CLK_PB4 SILABS_DBUS_USART1_CLK(0x1, 0x4)
2021
#define USART1_TX_PA0 SILABS_DBUS_USART1_TX(0x0, 0x0)
2022
#define USART1_TX_PA1 SILABS_DBUS_USART1_TX(0x0, 0x1)
2023
#define USART1_TX_PA2 SILABS_DBUS_USART1_TX(0x0, 0x2)
2024
#define USART1_TX_PA3 SILABS_DBUS_USART1_TX(0x0, 0x3)
2025
#define USART1_TX_PA4 SILABS_DBUS_USART1_TX(0x0, 0x4)
2026
#define USART1_TX_PA5 SILABS_DBUS_USART1_TX(0x0, 0x5)
2027
#define USART1_TX_PA6 SILABS_DBUS_USART1_TX(0x0, 0x6)
2028
#define USART1_TX_PA7 SILABS_DBUS_USART1_TX(0x0, 0x7)
2029
#define USART1_TX_PA8 SILABS_DBUS_USART1_TX(0x0, 0x8)
2030
#define USART1_TX_PB0 SILABS_DBUS_USART1_TX(0x1, 0x0)
2031
#define USART1_TX_PB1 SILABS_DBUS_USART1_TX(0x1, 0x1)
2032
#define USART1_TX_PB2 SILABS_DBUS_USART1_TX(0x1, 0x2)
2033
#define USART1_TX_PB3 SILABS_DBUS_USART1_TX(0x1, 0x3)
2034
#define USART1_TX_PB4 SILABS_DBUS_USART1_TX(0x1, 0x4)
2035
#define USART1_CTS_PA0 SILABS_DBUS_USART1_CTS(0x0, 0x0)
2036
#define USART1_CTS_PA1 SILABS_DBUS_USART1_CTS(0x0, 0x1)
2037
#define USART1_CTS_PA2 SILABS_DBUS_USART1_CTS(0x0, 0x2)
2038
#define USART1_CTS_PA3 SILABS_DBUS_USART1_CTS(0x0, 0x3)
2039
#define USART1_CTS_PA4 SILABS_DBUS_USART1_CTS(0x0, 0x4)
2040
#define USART1_CTS_PA5 SILABS_DBUS_USART1_CTS(0x0, 0x5)
2041
#define USART1_CTS_PA6 SILABS_DBUS_USART1_CTS(0x0, 0x6)
2042
#define USART1_CTS_PA7 SILABS_DBUS_USART1_CTS(0x0, 0x7)
2043
#define USART1_CTS_PA8 SILABS_DBUS_USART1_CTS(0x0, 0x8)
2044
#define USART1_CTS_PB0 SILABS_DBUS_USART1_CTS(0x1, 0x0)
2045
#define USART1_CTS_PB1 SILABS_DBUS_USART1_CTS(0x1, 0x1)
2046
#define USART1_CTS_PB2 SILABS_DBUS_USART1_CTS(0x1, 0x2)
2047
#define USART1_CTS_PB3 SILABS_DBUS_USART1_CTS(0x1, 0x3)
2048
#define USART1_CTS_PB4 SILABS_DBUS_USART1_CTS(0x1, 0x4)
2049
2050
#define ABUS_AEVEN0_IADC0 SILABS_ABUS(0x0, 0x0, 0x1)
2051
#define ABUS_AEVEN0_ACMP0 SILABS_ABUS(0x0, 0x0, 0x2)
2052
#define ABUS_AEVEN1_IADC0 SILABS_ABUS(0x0, 0x1, 0x1)
2053
#define ABUS_AEVEN1_ACMP0 SILABS_ABUS(0x0, 0x1, 0x2)
2054
#define ABUS_AODD0_IADC0 SILABS_ABUS(0x0, 0x2, 0x1)
2055
#define ABUS_AODD0_ACMP0 SILABS_ABUS(0x0, 0x2, 0x2)
2056
#define ABUS_AODD1_IADC0 SILABS_ABUS(0x0, 0x3, 0x1)
2057
#define ABUS_AODD1_ACMP0 SILABS_ABUS(0x0, 0x3, 0x2)
2058
#define ABUS_BEVEN0_IADC0 SILABS_ABUS(0x1, 0x0, 0x1)
2059
#define ABUS_BEVEN0_ACMP0 SILABS_ABUS(0x1, 0x0, 0x2)
2060
#define ABUS_BEVEN1_IADC0 SILABS_ABUS(0x1, 0x1, 0x1)
2061
#define ABUS_BEVEN1_ACMP0 SILABS_ABUS(0x1, 0x1, 0x2)
2062
#define ABUS_BODD0_IADC0 SILABS_ABUS(0x1, 0x2, 0x1)
2063
#define ABUS_BODD0_ACMP0 SILABS_ABUS(0x1, 0x2, 0x2)
2064
#define ABUS_BODD1_IADC0 SILABS_ABUS(0x1, 0x3, 0x1)
2065
#define ABUS_BODD1_ACMP0 SILABS_ABUS(0x1, 0x3, 0x2)
2066
#define ABUS_CDEVEN0_IADC0 SILABS_ABUS(0x2, 0x0, 0x1)
2067
#define ABUS_CDEVEN0_ACMP0 SILABS_ABUS(0x2, 0x0, 0x2)
2068
#define ABUS_CDEVEN1_IADC0 SILABS_ABUS(0x2, 0x1, 0x1)
2069
#define ABUS_CDEVEN1_ACMP0 SILABS_ABUS(0x2, 0x1, 0x2)
2070
#define ABUS_CDODD0_IADC0 SILABS_ABUS(0x2, 0x2, 0x1)
2071
#define ABUS_CDODD0_ACMP0 SILABS_ABUS(0x2, 0x2, 0x2)
2072
#define ABUS_CDODD1_IADC0 SILABS_ABUS(0x2, 0x3, 0x1)
2073
#define ABUS_CDODD1_ACMP0 SILABS_ABUS(0x2, 0x3, 0x2)
2074
2075
#endif
/* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG29_PINCTRL_H_ */
silabs-pinctrl-dbus.h
include
zephyr
dt-bindings
pinctrl
silabs
xg29-pinctrl.h
Generated on Sun May 4 2025 13:59:46 for Zephyr Project API by
1.9.8
1.9.8