CONFIG_2ND_LVL_ISR_TBL_OFFSET¶

Offset in _sw_isr_table for level 2 interrupts

Type: int

Help¶

This is the offset in _sw_isr_table, the generated ISR handler table,
where storage for 2nd level interrupt ISRs begins. This is
typically allocated after ISRs for level 1 interrupts.

Direct dependencies¶

(Includes any dependencies from ifs and menus.)

Defaults¶

21
21
21
21
21
32
12
12
12
12
12
32
12
12
12
12
12
0

Kconfig definitions¶

At <Zephyr Boards>/xtensa/intel_adsp_cavs15/Kconfig.defconfig:32

Included via Kconfig:8 → Kconfig.zephyr:22

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 21
    depends on BOARD_INTEL_ADSP_CAVS15

At <Zephyr Boards>/xtensa/intel_adsp_cavs18/Kconfig.defconfig:32

Included via Kconfig:8 → Kconfig.zephyr:22

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 21
    depends on BOARD_INTEL_ADSP_CAVS18

At <Zephyr Boards>/xtensa/intel_adsp_cavs20/Kconfig.defconfig:32

Included via Kconfig:8 → Kconfig.zephyr:22

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 21
    depends on BOARD_INTEL_ADSP_CAVS20

At <Zephyr Boards>/xtensa/intel_adsp_cavs25/Kconfig.defconfig:32

Included via Kconfig:8 → Kconfig.zephyr:22

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 21
    depends on BOARD_INTEL_ADSP_CAVS25

At <Zephyr Boards>/xtensa/intel_s1000_crb/Kconfig.defconfig:38

Included via Kconfig:8 → Kconfig.zephyr:22

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 21
    depends on BOARD_INTEL_S1000_CRB

At <Zephyr SoC>/riscv/openisa_rv32m1/Kconfig.defconfig:52

Included via Kconfig:8 → Kconfig.zephyr:25 → <BuildDir>/kconfig/Kconfig.soc.defconfig:1

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 32
    depends on MULTI_LEVEL_INTERRUPTS && SOC_OPENISA_RV32M1_RISCV32

At <Zephyr SoC>/riscv/riscv-privilege/andes_v5/Kconfig.defconfig.series:36

Included via Kconfig:8 → Kconfig.zephyr:25 → <BuildDir>/kconfig/Kconfig.soc.defconfig:1 → <Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 12
    depends on SOC_SERIES_RISCV_ANDES_V5

At <Zephyr SoC>/riscv/riscv-privilege/miv/Kconfig.defconfig.series:23

Included via Kconfig:8 → Kconfig.zephyr:25 → <BuildDir>/kconfig/Kconfig.soc.defconfig:1 → <Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 12
    depends on SOC_SERIES_RISCV32_MIV

At <Zephyr SoC>/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series:23

Included via Kconfig:8 → Kconfig.zephyr:25 → <BuildDir>/kconfig/Kconfig.soc.defconfig:1 → <Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 12
    depends on SOC_SERIES_RISCV_SIFIVE_FREEDOM

At <Zephyr SoC>/riscv/riscv-privilege/starfive_jh71xx/Kconfig.defconfig.series:24

Included via Kconfig:8 → Kconfig.zephyr:25 → <BuildDir>/kconfig/Kconfig.soc.defconfig:1 → <Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 12
    depends on SOC_SERIES_STARFIVE_JH71XX

At <Zephyr SoC>/riscv/riscv-privilege/virt/Kconfig.defconfig.series:24

Included via Kconfig:8 → Kconfig.zephyr:25 → <BuildDir>/kconfig/Kconfig.soc.defconfig:1 → <Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 12
    depends on SOC_SERIES_RISCV_VIRT

At <Zephyr SoC>/riscv/openisa_rv32m1/Kconfig.defconfig:52

Included via Kconfig:8 → Kconfig.zephyr:27

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 32
    depends on MULTI_LEVEL_INTERRUPTS && SOC_OPENISA_RV32M1_RISCV32

At <Zephyr SoC>/riscv/riscv-privilege/andes_v5/Kconfig.defconfig.series:36

Included via Kconfig:8 → Kconfig.zephyr:27 → <Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 12
    depends on SOC_SERIES_RISCV_ANDES_V5

At <Zephyr SoC>/riscv/riscv-privilege/miv/Kconfig.defconfig.series:23

Included via Kconfig:8 → Kconfig.zephyr:27 → <Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 12
    depends on SOC_SERIES_RISCV32_MIV

At <Zephyr SoC>/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series:23

Included via Kconfig:8 → Kconfig.zephyr:27 → <Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 12
    depends on SOC_SERIES_RISCV_SIFIVE_FREEDOM

At <Zephyr SoC>/riscv/riscv-privilege/starfive_jh71xx/Kconfig.defconfig.series:24

Included via Kconfig:8 → Kconfig.zephyr:27 → <Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 12
    depends on SOC_SERIES_STARFIVE_JH71XX

At <Zephyr SoC>/riscv/riscv-privilege/virt/Kconfig.defconfig.series:24

Included via Kconfig:8 → Kconfig.zephyr:27 → <Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_ISR_TBL_OFFSET
    int
    default 12
    depends on SOC_SERIES_RISCV_VIRT

At <Zephyr Driver>/interrupt_controller/Kconfig.multilevel:36

Included via Kconfig:8 → Kconfig.zephyr:42 → <Zephyr Driver>/Kconfig:28 → <Zephyr Driver>/interrupt_controller/Kconfig:48

Menu path: (Top) → Device Drivers → Interrupt Controllers → Multi-level interrupt support → Second-level interrupt support

config 2ND_LVL_ISR_TBL_OFFSET
    int "Offset in _sw_isr_table for level 2 interrupts"
    default 0
    depends on 2ND_LEVEL_INTERRUPTS
    help
      This is the offset in _sw_isr_table, the generated ISR handler table,
      where storage for 2nd level interrupt ISRs begins. This is
      typically allocated after ISRs for level 1 interrupts.

(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)