CONFIG_MCG_FRDIV

FLL external reference divider

FLL external reference divider

Type: int

Help

Selects the amount to divide down the external reference clock for the
FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625
kHz.

Help

Selects the amount to divide down the external reference clock for the
FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625
kHz.

Direct dependencies

BOARD_FRDM_KL25Z || BOARD_FRDM_KW41Z || BOARD_HEXIWEAR_KW40Z || (HAS_MCG && SOC_FAMILY_KINETIS) || (HAS_MCG && SOC_FAMILY_KINETIS)

(Includes any dependencies from ifs and menus.)

Defaults

• 5

• 5

• 5

• 0

• 0

Kconfig definitions

At <Zephyr Boards>/arm/frdm_kl25z/Kconfig.defconfig:20

Included via Kconfig:8 → Kconfig.zephyr:22

Menu path: (Top)

config MCG_FRDIV
    int
    default 5
    depends on BOARD_FRDM_KL25Z

---

At <Zephyr Boards>/arm/frdm_kw41z/Kconfig.defconfig:14

Included via Kconfig:8 → Kconfig.zephyr:22

Menu path: (Top)

config MCG_FRDIV
    int
    default 5
    depends on BOARD_FRDM_KW41Z

---

At <Zephyr Boards>/arm/hexiwear_kw40z/Kconfig.defconfig:14

Included via Kconfig:8 → Kconfig.zephyr:22

Menu path: (Top)

config MCG_FRDIV
    int
    default 5
    depends on BOARD_HEXIWEAR_KW40Z

---

At <Zephyr SoC>/arm/nxp_kinetis/Kconfig:94

Included via Kconfig:8 → Kconfig.zephyr:38 → <Zephyr SoC>/Kconfig:15 → <BuildDir>/kconfig/Kconfig.soc.arch:2

Menu path: (Top) → Hardware Configuration

config MCG_FRDIV
    int "FLL external reference divider"
    range 0 7
    default 0
    depends on HAS_MCG && SOC_FAMILY_KINETIS
    help
      Selects the amount to divide down the external reference clock for the
      FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625
      kHz.

---

At <Zephyr SoC>/arm/nxp_kinetis/Kconfig:94

Included via Kconfig:8 → Kconfig.zephyr:38 → <Zephyr SoC>/Kconfig:18

Menu path: (Top) → Hardware Configuration

config MCG_FRDIV
    int "FLL external reference divider"
    range 0 7
    default 0
    depends on HAS_MCG && SOC_FAMILY_KINETIS
    help
      Selects the amount to divide down the external reference clock for the
      FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625
      kHz.

(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)