#include <xtensa/config/core-isa.h>
#include <zephyr/toolchain.h>
#include <zephyr/sys/util.h>
#include <zephyr/debug/sparse.h>

Macros
#define	ARCH_XTENSA_SET_RPO_TLB()

Functions
static void __sparse_cache *	arch_xtensa_cached_ptr (void *ptr)
	Return cached pointer to a RAM address. More...

static void *	arch_xtensa_uncached_ptr (void __sparse_cache *ptr)
	Return uncached pointer to a RAM address. More...

Macro Definition Documentation

◆ ARCH_XTENSA_SET_RPO_TLB

#define ARCH_XTENSA_SET_RPO_TLB ( )

Value:

        do {                            \
        register uint32_t addr = 0, addrincr = 0x20000000;      \
        FOR_EACH(_SET_ONE_TLB, (;), 0, 1, 2, 3, 4, 5, 6, 7);    \
} while (0)

Function Documentation

◆ arch_xtensa_cached_ptr()

static void __sparse_cache * arch_xtensa_cached_ptr ( void * ptr )

inlinestatic

Return cached pointer to a RAM address.

The Xtensa coherence architecture maps addressable RAM twice, in two different 512MB regions whose L1 cache settings can be controlled independently. So for any given pointer, it is possible to convert it to and from a cached version.

This function takes a pointer to any addressable object (either in cacheable memory or not) and returns a pointer that can be used to refer to the same memory through the L1 data cache. Data read through the resulting pointer will reflect locally cached values on the current CPU if they exist, and writes will go first into the cache and be written back later.

See also: arch_xtensa_uncached_ptr()

Parameters

ptr	A pointer to a valid C object

Returns: A pointer to the same object via the L1 dcache

◆ arch_xtensa_uncached_ptr()

static void * arch_xtensa_uncached_ptr ( void __sparse_cache * ptr )

inlinestatic

Return uncached pointer to a RAM address.