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◆ STM32_CLOCK_BUS_AHB1
| #define STM32_CLOCK_BUS_AHB1 0x030 |
◆ STM32_CLOCK_BUS_AHB2
| #define STM32_CLOCK_BUS_AHB2 0x034 |
◆ STM32_CLOCK_BUS_AHB3
| #define STM32_CLOCK_BUS_AHB3 0x038 |
◆ STM32_CLOCK_BUS_APB1
| #define STM32_CLOCK_BUS_APB1 0x040 |
◆ STM32_CLOCK_BUS_APB2
| #define STM32_CLOCK_BUS_APB2 0x044 |
◆ STM32_CLOCK_BUS_APB3
| #define STM32_CLOCK_BUS_APB3 0x0A8 |
◆ STM32_PERIPH_BUS_MAX
◆ STM32_PERIPH_BUS_MIN
◆ STM32_SRC_PLL_P
| #define STM32_SRC_PLL_P 0x001 |
Domain clocks PLL clock outputs
◆ STM32_SRC_PLL_Q
| #define STM32_SRC_PLL_Q 0x002 |
◆ STM32_SRC_PLL_R
| #define STM32_SRC_PLL_R 0x003 |