stm32l0_clock.h

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/*
 * Copyright (c) 2022 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_
 
#define STM32_CLOCK_BUS_IOP     0x02c
#define STM32_CLOCK_BUS_AHB1    0x030
#define STM32_CLOCK_BUS_APB2    0x034
#define STM32_CLOCK_BUS_APB1    0x038
 
#define STM32_PERIPH_BUS_MIN    STM32_CLOCK_BUS_IOP
#define STM32_PERIPH_BUS_MAX    STM32_CLOCK_BUS_APB1
 
/* RM0367, §7.3.20 Clock configuration register (RCC_CCIPR) */
 
#define STM32_SRC_HSE           0x001
#define STM32_SRC_LSE           0x002
#define STM32_SRC_LSI           0x003
#define STM32_SRC_HSI           0x004
#define STM32_SRC_SYSCLK        0x005
#define STM32_SRC_PCLK          0x006
 
#define STM32_CLOCK_REG_MASK    0xFFU
#define STM32_CLOCK_REG_SHIFT   0U
#define STM32_CLOCK_SHIFT_MASK  0x1FU
#define STM32_CLOCK_SHIFT_SHIFT 8U
#define STM32_CLOCK_MASK_MASK   0x7U
#define STM32_CLOCK_MASK_SHIFT  13U
#define STM32_CLOCK_VAL_MASK    0x7U
#define STM32_CLOCK_VAL_SHIFT   16U
 
#define STM32_CLOCK(val, mask, shift, reg)                                      \
        ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |            \
         (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |      \
         (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |         \
         (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
 
#define CCIPR_REG               0x4C
 
#define USART1_SEL(val)         STM32_CLOCK(val, 3, 0, CCIPR_REG)
#define USART2_SEL(val)         STM32_CLOCK(val, 3, 2, CCIPR_REG)
#define LPUART1_SEL(val)        STM32_CLOCK(val, 3, 10, CCIPR_REG)
#define I2C1_SEL(val)           STM32_CLOCK(val, 3, 12, CCIPR_REG)
#define I2C3_SEL(val)           STM32_CLOCK(val, 3, 16, CCIPR_REG)
#define LPTIM1_SEL(val)         STM32_CLOCK(val, 3, 18, CCIPR_REG)
#define HSI48_SEL(val)          STM32_CLOCK(val, 1, 26, CCIPR_REG)
 
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_ */